2010 International Conference on Field Programmable Logic and Applications最新文献_第5页

Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic 利用免进位算法在fpga上合成浮点加法簇

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.15

Amit Verma, A. K. Verma, H. Parandeh-Afshar, P. Brisk, P. Ienne

引用次数: 9

Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers 利用路由器的局部和动态重构提高多层片上网络的QoS

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.53

Leandro Möller, Peter Fischer, F. Moraes, L. Indrusiak, M. Glesner

{"title":"Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers","authors":"Leandro Möller, Peter Fischer, F. Moraes, L. Indrusiak, M. Glesner","doi":"10.1109/FPL.2010.53","DOIUrl":"https://doi.org/10.1109/FPL.2010.53","url":null,"abstract":"Networks-on-Chip (NoC) allow several data transfers to occur in parallel and are indeed the communication infra-structure of future hundred-cores Systems-on-Chip (SoCs). However, if specialized modules are sending data at full speed to the NoC, Quality of Service (QoS) can be no longer guaranteed. This work presents a multi-layer mesh NoC approach to improve the QoS of such communication hungry SoCs. While one mesh layer is fixed in the system for control purposes, other data layers can be configured at runtime to provide the desired data throughput required by the application. This is accomplished by partially and dynamically reconfiguring the data layer routers. Arbitration algorithms, routing algorithms and huge crossbars are removed from the data layer routers, because all data routers in the path a configured accordingly before its utilization. A SoC following this idea was prototyped in a Virtex-4 FPGA and the Early Access Partial Flow was used to partially and dynamically reconfigure the NoC. We show that 120 (5!) different configurations are needed for each reconfigurable router with 5 bidirectional ports. Each configuration requires 33KB of memory and occupies 32 CLBs of area.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"241 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116061309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains 通过加性进位链的自动逻辑映射增强FPGA器件性能

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.70

Thomas B. Preußer, R. Spallek

{"title":"Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains","authors":"Thomas B. Preußer, R. Spallek","doi":"10.1109/FPL.2010.70","DOIUrl":"https://doi.org/10.1109/FPL.2010.70","url":null,"abstract":"This paper presents an approach to the automatic mapping of arbitrary combinational circuits to the arithmetic carry-chain structures widely available in modern FPGAs. This capability is highly valuable as it enables the utilization of these fast special-purpose structures for general-purpose logic. The described approach is both automatic and generally applicable to all carry-chain architectures designed for binary addition. It, thus, lifts severe constraints left by previous works. It helps to reduce the pressure on the general-purpose routing resources and accelerates critical logic paths. The proposed mapping is further shown to enhance the logic capability of a logic block containing a k-input lookup table (k-LUT) to implement many (k+1)-input functions on common FPGA architectures. This, in particular, also applies to all logic functions with a non-inverting path as introduced by Anderson and Wang. This makes their envisioned gains in logic density achievable even on current devices without requiring their architectural extension. The benefits of the carry-chain mapping are experimentally evaluated on the basis of combinational MCNC benchmarks. It is shown how carry chains can be recovered within a functional standard mapping and that a device mapping aware of carry chains achieves a reduction of the combinational delay of about a 20 percent.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114842624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

GPU Versus FPGA for High Productivity Computing GPU与FPGA的高生产率计算

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.32

D. H. Jones, Adam Powell, C. Bouganis, P. Cheung

引用次数: 59

Thermal Gradient Aware Clock Skew Scheduling for FPGAs fpga热梯度感知时钟倾斜调度

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.29

Sungmin Bae, N. Vijaykrishnan

引用次数: 1

Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options 奇异期权定价的可重构控制变量蒙特卡罗设计

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.46

Anson H. T. Tse, David B. Thomas, K. H. Tsoi, W. Luk

引用次数: 18

First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells 具有FeRAM单元的真正电源门控可重构逻辑芯片的第一个原型

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.67

Masahiro Koga, M. Iida, M. Amagasaki, Yoshinobu Ichida, Mitsuro Saji, J. Iida, T. Sueyoshi

{"title":"First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells","authors":"Masahiro Koga, M. Iida, M. Amagasaki, Yoshinobu Ichida, Mitsuro Saji, J. Iida, T. Sueyoshi","doi":"10.1109/FPL.2010.67","DOIUrl":"https://doi.org/10.1109/FPL.2010.67","url":null,"abstract":"An advantage of a RLD (Reconfigurable logic device) such as an FPGA (Field programmable gate array) is that it can be customized after being manufactured. However, there is a problem related to standby power when using it in SoC used in embedded systems. Power gating, which is one of the power reduction techniques, is difficult to use in SRAM-based RLDs because of the high overhead — data hibernation and reconfiguration time — and SRAM being volatile. In this paper, we describe a chip that we developed — are configurable logic chip based on FeRAM (Ferroelectric random access memory) technology. The chip employs island-style routing architecture and uses a variable grain logic cell as a logic block. A NV-FF (Non-Volatile FlipFlop), which contains FeRAM, aFF, and power-gating control circuits, is used as configuration memory. The NV-FF can transmit data between FeRAM and FF automatically when power to the chip is turned off/on. Thus, chip-level power gating is possible. The hibernate/restore time is less than 1 ms. The chip has 18 x 18 logic blocks and an area of 54.76 mm2.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134568677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

A Cost-Effective Technique for Mapping BLUTs to QLUTs in FPGAs fpga中blt到qlut的一种经济有效的映射技术

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.72

M. Ritt, C. Lisbôa, L. Carro, C. Lazzari

引用次数: 6

Dynamically Reconfigurable Vision-Chip Architecture 动态可重构视觉芯片架构

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.101

Maki Yasuda, Minoru Watanabe

引用次数: 7

An Interior Point Optimization Solver for Real Time Inter-frame Collision Detection: Exploring Resource-Accuracy-Platform Tradeoffs 实时帧间碰撞检测的内部点优化求解器:探索资源-精度-平台的权衡

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.31

Brian Leung, Chih-Hung Wu, S. Memik, Sanjay Mehrotra

{"title":"An Interior Point Optimization Solver for Real Time Inter-frame Collision Detection: Exploring Resource-Accuracy-Platform Tradeoffs","authors":"Brian Leung, Chih-Hung Wu, S. Memik, Sanjay Mehrotra","doi":"10.1109/FPL.2010.31","DOIUrl":"https://doi.org/10.1109/FPL.2010.31","url":null,"abstract":"We present and compare implementations of an affine interior-point algorithm for real-time collision detection on a GPGPU and an FPGA. This particular interior-point algorithm is distinguished from other collision detection methods by its ability to perform detection between pairs of objects undergoing fast rotational and translational movement. This enables inter-frame collision detection, i.e. collision that might occur during the transition from one frame to another. In our design for the FPGA, we implemented the algorithm both in single-precision floating point and 32-bit fixed point and analyzed the trade-off between resource usage, data accuracy/precision, and system efficiency. Then, we compare them to a floating point implementation on a GPGPU using CUDA. With an object resolution of 45 vertices (45 vertices representing each polyhedral object), our FPGA implementation processes 1562 frames/sec for floating point and 1350 frames/second for fixed point and offers an 11x speedup over the GPGPU implementation. With object resolutions greater than 242 vertices, our GPGPU implementation outperforms our FPGA implementations.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129361486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9