2010 International Conference on Field Programmable Logic and Applications最新文献

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Degradation Analysis and Mitigation in FPGAs fpga的退化分析与缓解
Edward A. Stott, Justin S. J. Wong, P. Cheung
{"title":"Degradation Analysis and Mitigation in FPGAs","authors":"Edward A. Stott, Justin S. J. Wong, P. Cheung","doi":"10.1109/FPL.2010.88","DOIUrl":"https://doi.org/10.1109/FPL.2010.88","url":null,"abstract":"FPGAs are powerful platforms for investigating impending challenges associated with process scaling, such as variation and degradation. Their versatility allows us to gather empirical data and evaluate novel solutions. We carried out accelerated-life tests on modern FPGA devices and obtained a useful characterisation of the ageing processes that afflict them. We also quantified the potential benefits of three degradation mitigation strategies based on exploiting spare logic and interconnect resources. The work helps cement the role of reconfigurable logic as a vitally-important technology in the face of the uncertainties of future process scaling.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128274505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
Rapid Prototyping of Radiation-Tolerant Embedded Systems on FPGA 基于FPGA的耐辐射嵌入式系统快速原型设计
Felipe Restrepo-Calle, A. Martínez-Álvarez, F. R. Palomo, H. Guzmán-Miranda, M. Aguirre, S. Cuenca-Asensi
{"title":"Rapid Prototyping of Radiation-Tolerant Embedded Systems on FPGA","authors":"Felipe Restrepo-Calle, A. Martínez-Álvarez, F. R. Palomo, H. Guzmán-Miranda, M. Aguirre, S. Cuenca-Asensi","doi":"10.1109/FPL.2010.71","DOIUrl":"https://doi.org/10.1109/FPL.2010.71","url":null,"abstract":"Technological advances of Field Programmable Gate Array (FPGA) are making that this technology becomes the most preferred platform for the rapid prototyping of highly integrated digital systems. In addition, protection of processor-based systems to mitigate the harmful effects of radiation-induced upset events is gaining importance while technology shrinks. In this context, the main contribution of this work is a novel rapid prototyping approach for the co-design of dependable embedded systems using FPGA. This is supported by a hardening platform that allows combining software-only fault-tolerance techniques with hardware-only approaches, representing several trade-offs among design constraints, reliability and cost. As case study, several radiation-tolerant embedded systems have been developed based on a technology-independent version of the Picoblaze processor.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129469786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Using Hard Macros to Reduce FPGA Compilation Time 使用硬宏减少FPGA编译时间
C. Lavin, M. Padilla, Subhrashankha Ghosh, B. Nelson, B. Hutchings, M. Wirthlin
{"title":"Using Hard Macros to Reduce FPGA Compilation Time","authors":"C. Lavin, M. Padilla, Subhrashankha Ghosh, B. Nelson, B. Hutchings, M. Wirthlin","doi":"10.1109/FPL.2010.90","DOIUrl":"https://doi.org/10.1109/FPL.2010.90","url":null,"abstract":"The FPGA compilation process (synthesis, map, placement, routing) is a time-consuming process that limits designer productivity. Compilation time can be reduced by using pre-compiled circuit blocks (hard macros). Hard macros consist of previously synthesized, mapped, placed and routed circuitry that can be relatively placed with short tool runtimes and that make it possible to reuse previous computational effort. Two experiments were performed to demonstrate feasibility that hard macros can reduce compilation time. These experiments demonstrated that an augmented Xilinx flow designed specifically to support hard macros can reduce overall compilation time by 3x. Though the process of incorporating hard macros in designs is currently manual and error-prone, it can be automated to create compilation flows with much lower compilation time.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124742817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Accurate Time-to-Digital Converter Based on Xilinx's Digital Clock Managers 基于赛灵思数字时钟管理器的精确时间-数字转换器
2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.100
Ángel Quirós-Olozábal, M. Chacón, J. Guerrero-Rodríguez
{"title":"Accurate Time-to-Digital Converter Based on Xilinx's Digital Clock Managers","authors":"Ángel Quirós-Olozábal, M. Chacón, J. Guerrero-Rodríguez","doi":"10.1109/FPL.2010.100","DOIUrl":"https://doi.org/10.1109/FPL.2010.100","url":null,"abstract":"This paper presents an accurate and simple delay measurement method based on Xilinx's Digital Clock Managers. Particularly, variable phase shift is the modules’ capability exploited in our approach. This method enables the implementation of a time-to-digital converter that achieves a resolution of 200ps on a Xilinx's Virtex or Spartan-3 FPGA without requiring manual placement & routing, nor an external calibration process. This circuit can be used in any application that demands a precise measurement of a static delay.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125119643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Flexible and Modular Support for Timing Functions in High Performance Networking Acceleration 对高性能网络加速中定时功能的灵活和模块化支持
2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.102
Christopher E. Neely, G. Brebner, Weijia Shang
{"title":"Flexible and Modular Support for Timing Functions in High Performance Networking Acceleration","authors":"Christopher E. Neely, G. Brebner, Weijia Shang","doi":"10.1109/FPL.2010.102","DOIUrl":"https://doi.org/10.1109/FPL.2010.102","url":null,"abstract":"Field programmable logic is increasingly used to provide the high performance and flexible acceleration needed for network processing functions at multiple gigabit/second rates. Almost all such functions feature the use of clocks and timers in control and/or data roles, and these are typically implemented in an ad hoc manner. This paper introduces a set of three configurable timing modules that are based on abstractions of the prevalent timing paradigms observed in network protocols. The modules fit within the experimental ShapeUp methodology for modular FPGA-based system design, and so can be easily integrated with other modules that are tailored for specific networking functions. The use and benefits of the new modular approach are demonstrated by an example of a flexible FPGA reference design that has been made available for real-life use by telecommunication equipment providers.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125813152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Exploiting Dynamic Reconfiguration for FPGA Based Network Intrusion Detection Systems 基于FPGA的网络入侵检测系统动态重构研究
S. Pontarelli, C. Greco, Enrico Nobile, S. Teofili, G. Bianchi
{"title":"Exploiting Dynamic Reconfiguration for FPGA Based Network Intrusion Detection Systems","authors":"S. Pontarelli, C. Greco, Enrico Nobile, S. Teofili, G. Bianchi","doi":"10.1109/FPL.2010.13","DOIUrl":"https://doi.org/10.1109/FPL.2010.13","url":null,"abstract":"A Network Intrusion Detection System (NIDS) inspects the traffic flowing in a network to detect malicious content such as spam, viruses, and so on. Hardware based solutions appear necessary to face the performance requirements emerging when the goal is to deploy such systems in high speed network scenarios. However, the appropriate choice of the hardware platform is believed to be subject to at least two requirements, usually considered independent each other: i) it needs to be reprogrammable, in order to update the intrusion detection rules each time a new threat arises, and ii) it must be capable of containing the typically very large set of rules of existing NIDSs. The goal of this paper is to show that reprogrammability can be further exploited to reduce the resource requirements for the chosen platform. Specifically, we propose an FPGA-based solution that classifies and dispatches traffic to elastic buffers, connecting one buffer at a time to a dynamically reconfigurable rule matching core. This core supports only the appropriate subset of detection rules. A worst-case analysis shows that the saving in hardware resources is achieved with a relatively small buffer space, currently available in cheap, low end, FPGA boards, with no impairment on the resulting throughput.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122459657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs 一种基于总线的SoC架构,可在可重构fpga上灵活放置模块
Andreas Oetken, S. Wildermann, J. Teich, Dirk Koch
{"title":"A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs","authors":"Andreas Oetken, S. Wildermann, J. Teich, Dirk Koch","doi":"10.1109/FPL.2010.54","DOIUrl":"https://doi.org/10.1109/FPL.2010.54","url":null,"abstract":"This paper proposes an FPGA-based System-on-Chip (SoC) architecture with support for dynamic runtime reconfiguration. The SoC is divided into two parts, the static embedded CPU sub-system and the dynamically reconfigurable part. An additional bus system connects the embedded CPU sub-system with modules within the dynamic area, offering a flexible way to communicate among all SoC components. This makes it possible to implement a reconfigurable design with support for free module placement. An enhanced memory access method is included for high-speed access to an external memory. The dynamic part includes a streaming technology which implements a direct connection between reconfigurable modules. The paper describes the architecture and shows the advantages in a smart camera case study.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"9 29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125872438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 50
Implementing Rainbow Tables in High-End FPGAs for Super-Fast Password Cracking 在高端fpga中实现彩虹表,实现超快速密码破解
2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.120
Kostas Theocharoulis, I. Papaefstathiou, C. Manifavas
{"title":"Implementing Rainbow Tables in High-End FPGAs for Super-Fast Password Cracking","authors":"Kostas Theocharoulis, I. Papaefstathiou, C. Manifavas","doi":"10.1109/FPL.2010.120","DOIUrl":"https://doi.org/10.1109/FPL.2010.120","url":null,"abstract":"One of the most efficient methods for cracking passwords, which are hashed based on different cryptographic algorithms, is the one based on “Rainbow Tables”. Those lookup tables offer an almost optimal time-memory tradeoff in the process of recovering the plaintext password from a password hash, generated by a cryptographic hash function. In this paper, the first known such generic system is demonstrated. It is implemented in a state-of-the-art reconfigurable device that cracks passwords, which are encrypted with a number of different cryptographic algorithms. The proposed FPGA-based system is up to 1000 times faster than the corresponding software approach. This is achieved by using a highly parallel architecture employing a fine-grained pipeline.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124119698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Erlang Inspired Hardware 受Erlang启发的硬件
Paulo A. Ferreira, J. Ferreira, J. Alves
{"title":"Erlang Inspired Hardware","authors":"Paulo A. Ferreira, J. Ferreira, J. Alves","doi":"10.1109/FPL.2010.56","DOIUrl":"https://doi.org/10.1109/FPL.2010.56","url":null,"abstract":"The Erlang programming language is a concurrency oriented functional language, based on the notion of independent processes and uses message passing for communication between processes. It is specially adapted to the realization of highly reliable distributed systems. In this paper it is analyzed the use of the Erlang's computational paradigm for the design and implementation of application specific heterogeneous computational systems. The main objective is to use for the low level implementation the same computational model used in high level view of the system. This will allow an easier and faster design space exploration and optimization.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127630753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique 利用时钟门控技术降低嵌入式DSP平台的功耗
A. Hermanek, M. Kunes, M. Tichý
{"title":"Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique","authors":"A. Hermanek, M. Kunes, M. Tichý","doi":"10.1109/FPL.2010.73","DOIUrl":"https://doi.org/10.1109/FPL.2010.73","url":null,"abstract":"The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGA based systems. The clock-gating techniques are used to reduce the total power of the system. To achieve this, we reduce clock power consumption of the system by switching-off the clock signal for the parts of system that are not used. The system presented in this paper is based on the main processor, extended with several reconfigurable accelerators. These accelerators extend the processor capabilities by several vector operations and can be reprogrammed in run-time. Clock gating, in our design, is used to switch the accelerators off when not used. As the accelerators can represent a major part of the system size, switching them off can significantly reduce the power consumption. We also propose the method for estimation of the reduction of power consumption that can be achieved using the clock-gating technique.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127885782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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