2010 International Conference on Field Programmable Logic and Applications最新文献_第3页

IP Based Configurable SIMD Massively Parallel SoC 基于IP的可配置SIMD大规模并行SoC

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.57

M. Baklouti, M. Abid, P. Marquet, J. Dekeyser

引用次数: 7

Reconfigurable Systems for the Zuker and Predator Algorithms for Secondary Structure Prediction of Genetic Data 用于遗传数据二级结构预测的Zuker和Predator算法的可重构系统

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.91

Miltiadis Smerdis, Panagiotis Dagritzikos, Grigorios Chrysos, E. Sotiriades, A. Dollas

引用次数: 1

Short-Circuits on FPGAs Caused by Partial Runtime Reconfiguration 部分运行时重构引起的fpga短路

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.117

Christian Beckhoff, Dirk Koch, J. Tørresen

引用次数: 45

Parallelizing FPGA Technology Mapping Using Graphics Processing Units (GPUs) 利用图形处理单元(gpu)并行化FPGA技术映射

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.33

Doris T. Chen, Deshanand P. Singh

引用次数: 9

FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers 使用lut和移位寄存器的fpga优化的均匀随机数生成器

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.25

David B. Thomas, W. Luk

引用次数: 52

FPGA Based Engines for Genetic and Memetic Algorithms 基于FPGA的遗传和模因算法引擎

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.58

P. V. Santos, J. Alves

引用次数: 10

Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA 基于FPGA的分层多时钟域高级综合低功耗设计

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.94

Ghizlane Lhairech-Lebreton, P. Coussy, E. Martin

引用次数: 18

Automation Framework for Large-Scale Regular Expression Matching on FPGA 基于FPGA的大规模正则表达式匹配自动化框架

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.21

Thilan Ganegedara, Y. Yang, V. Prasanna

{"title":"Automation Framework for Large-Scale Regular Expression Matching on FPGA","authors":"Thilan Ganegedara, Y. Yang, V. Prasanna","doi":"10.1109/FPL.2010.21","DOIUrl":"https://doi.org/10.1109/FPL.2010.21","url":null,"abstract":"We present an extensible automation framework for constructing and optimizing large-scale regular expression matching (REM) circuits on FPGA. Paralleling the technique used by software compilers, we divide our framework into two parts: a frontend that parses each PCRE-formatted regular expression (regex) into a modular non-deterministic finite automaton (RE-NFA), followed by a backend that generates the REM circuit design for a multi-pipeline architecture. With such organization, various pattern and circuit level optimizations can be applied to the frontend and backend, respectively. The multi-pipeline architecture utilizes both logic slices and on-chip BRAM for optimized character matching; in addition, it can be configured at compile-time to produce concurrent matching outputs from multiple RE-NFAs. Our framework prototype handles up to 64k \"regular\" regexes with arbitrary complexity and number of states, limited only by the hardware resources of the target device. Running on a commodity 2.3 GHz PC (AMD Opteron 1356), it takes less than a minute for the framework to convert ~1800 regexes used by the Snort IDS into RTL-level designs with optimized logic and memory usage. Such an automation framework could be invaluable to REM systems to update regex definitions with minimal human intervention.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133271069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Real-Time Classification of Multimedia Traffic Using FPGA 基于FPGA的多媒体流量实时分类

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.22

Weirong Jiang, M. Gokhale

{"title":"Real-Time Classification of Multimedia Traffic Using FPGA","authors":"Weirong Jiang, M. Gokhale","doi":"10.1109/FPL.2010.22","DOIUrl":"https://doi.org/10.1109/FPL.2010.22","url":null,"abstract":"Real-time classification of Internet traffic according to application types is vital for network management and surveillance. Identifying emerging applications based on well-known port numbers is no longer reliable. While deep packet inspection (DPI) solutions can be accurate, they require constant updates of signatures and become infeasible for encrypted payload especially in multimedia applications (e.g. Skype). Statistical approaches based on machine learning have thus been considered more promising and robust to encryption, privacy, protocol obfuscation, etc. However, the computation complexity of traffic classification using those statistical solutions is high, which prevents them being deployed in systems that need to manage Internet traffic in real time. This paper proposes a FPGA-based parallel architecture to accelerate the statistical identification of multimedia applications while maintaining high classification accuracy. Specifically, we base our design on the k-Nearest Neighbors (k-NN) algorithm which has been shown to be one of the most accurate machine learning algorithms for Internet traffic classification. To enable high-rate data streaming for real-time classification, we adopt the locality sensitive hashing (LSH) for approximate k-NN. The LSH scheme is carefully designed to achieve high accuracy while being efficient for implementation on FPGA. Processing components in the architecture are optimized to realize high throughput. Extensive experiments and FPGA implementation results show that our design can achieve high accuracy above 99% for classifying three main categories of multimedia applications from Internet traffic while sustaining 80 Gbps throughput for minimum size (40 bytes) packets.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121351998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 48

Self-Test and Adaptation for Random Variations in Reliability 信度随机变化的自检与自适应

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.47

K. Zick, J. Hayes

引用次数: 4