2010 International Conference on Field Programmable Logic and Applications最新文献_第2页

ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs ATHENa -硬件评估的自动化工具:使用fpga对加密硬件进行公平和全面的基准测试

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.86

K. Gaj, J. Kaps, Venkata Amirineni, M. Rogawski, Ekawat Homsirikamol, Benjamin Y. Brewster

{"title":"ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs","authors":"K. Gaj, J. Kaps, Venkata Amirineni, M. Rogawski, Ekawat Homsirikamol, Benjamin Y. Brewster","doi":"10.1109/FPL.2010.86","DOIUrl":"https://doi.org/10.1109/FPL.2010.86","url":null,"abstract":"A fair comparison of functionally equivalent digital system designs targeting FPGAs is a challenging and time consuming task. The results of the comparison depend on the inherent properties of competing algorithms, as well as on selected hardware architectures, implementation techniques, FPGA families, languages and tools. In this paper, we introduce an open-source environment, called ATHENa for fair, comprehensive, automated, and collaborative hardware benchmarking of algorithms belonging to the same class. As our first goal, we select the benchmarking of algorithms belonging to the area of cryptography. Algorithms from this area have been shown to achieve significant speed-ups and security gains compared to software when implemented in FPGAs. The capabilities of our environment are demonstrated using three examples: two different hardware architectures of the current cryptographic hash function standard, SHA-256, and one architecture of a candidate for the new standard, Fugue. All source codes, testbenches, and configuration files necessary to repeat experiments described in this paper are made available through the project web site.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132869405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 92

Control Techniques for Coupling a Coarse-Grain Reconfigurable Array with a Generic RISC Core 粗粒度可重构阵列与通用RISC内核耦合控制技术

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.12

F. Garzia, Waqar Hussain, J. Nurmi

{"title":"Control Techniques for Coupling a Coarse-Grain Reconfigurable Array with a Generic RISC Core","authors":"F. Garzia, Waqar Hussain, J. Nurmi","doi":"10.1109/FPL.2010.12","DOIUrl":"https://doi.org/10.1109/FPL.2010.12","url":null,"abstract":"This paper presents three different control techniques to couple a Coarse-Grain Reconfigurable Architecture (CGRA) with a generic RISC processor. In the architecture under study the CGRA, i.e., a coarse-grain array, works as co-processor and is used to accelerate a kernel selected by the application developer. The array is meant to perform the data processing operations of the kernel, while the RISC processor takes care of the control of the kernel global execution. The control techniques proposed here do not add any dedicated instructions to the ISA of the RISC processor, but are mostly based on load/store operations. The first method is the slowest one, in which the control operations are executed sequentially with the array processing. The second approach enables some parallelism between control operations and array processing. The parallelism is guaranteed by the replacement of a single control register with a two-register delay chain. The last approach is the fastest, which replaces the delay chain with a FIFO. In particular, a 64-point FFT test case shows that the last solution is 2.5X faster than the second one.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133047963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

SeqHive: A Reconfigurable Computer Cluster for Genome Re-sequencing SeqHive:用于基因组重测序的可重构计算机集群

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.121

Kristian Stevens, Henry Chen, T. Filiba, P. McMahon, Yun S. Song

{"title":"SeqHive: A Reconfigurable Computer Cluster for Genome Re-sequencing","authors":"Kristian Stevens, Henry Chen, T. Filiba, P. McMahon, Yun S. Song","doi":"10.1109/FPL.2010.121","DOIUrl":"https://doi.org/10.1109/FPL.2010.121","url":null,"abstract":"We demonstrate how Field Programmable Gate Arrays (FPGAs) may be used to address the computing challenges associated with assembling genome sequences from recent ultra-high-throughput sequencing technologies. Advances in sequencing technology allow researchers to generate immense amounts of raw data in the form of short reads with high error rates. A prerequisite to effectively utilizing this data for most applications is accurate alignment to a reference genome. While dynamic programming (DP) alignment algorithms are generally avoided on conventional architectures due to their computational complexity, they can be tailored for efficient implementation on systolic architectures. We describe and implement the first system capable of assembling large genomes using DP. We implemented application-specific DP algorithms for aligning data from ultra-high-throughput sequencers in a reconfigurable computing cluster. To obtain the necessary throughput while maintaining scoring integrity, we extended the compact encoding scheme of Lipton and Lopresti for our application. Each FPGA is capable of rapidly aligning multiple reads in parallel against a long reference genome. The reconfigurable cluster proves to be scalable and capable of processing real world datasets with a sustained performance of 11 tera cell updates per second. We examine the advantages and practicality of our system by benchmarking real genomic data from a large sequencing project. Our exhaustive validation confirms that application specific computing hardware can provide more accurate results than current heuristic methods and remain practical. While directly addressing the important problem of genomic assembly, particularly in circumstances where error rates or evolutionary divergence is high, the methods presented are also relevant to many other current applications for this type of data.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115649704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

An IEEE 754-2008 Decimal Parallel and Pipelined FPGA Floating-Point Multiplier 一种十进制并行流水线FPGA浮点乘法器

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.98

Malte Baesler, Sven-Ole Voigt, T. Teufel

引用次数: 12

FPGA Implementations of the Round Two SHA-3 Candidates 第二轮SHA-3候选算法的FPGA实现

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.84

Brian Baldwin, A. Byrne, Liang Lu, Mark Hamilton, Neil Hanley, Máire O’Neill, W. Marnane

引用次数: 101

Self-Aware Adaptation in FPGA-based Systems 基于fpga系统的自感知自适应

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.43

F. Sironi, Marco Triverio, H. Hoffmann, M. Maggio, M. Santambrogio

{"title":"Self-Aware Adaptation in FPGA-based Systems","authors":"F. Sironi, Marco Triverio, H. Hoffmann, M. Maggio, M. Santambrogio","doi":"10.1109/FPL.2010.43","DOIUrl":"https://doi.org/10.1109/FPL.2010.43","url":null,"abstract":"Self-Aware Adaptive computing systems are capable of adapting their behavior and resources thousands of times based on changing environmental conditions and demands. This allows them to automatically find the best way to accomplish a given goal with the resources at hand. This capability would benefit the full range of computer systems, from embedded devices to servers to supercomputers. Although such a system may seem rather far fetched, we believe that basic semiconductor technology, computer architecture and software systems have advanced to the point that the time is ripe to realize such a system. In this paper we present an implementation of an FPGA-based Self-Aware Adaptive computing system which blends techniques developed in different research fields, i.e, monitoring, decision making, and self-adaptation. The result is a system built on top of a set of enabling technology that proves the effectiveness of using Self-Aware Adaptive computing systems. We used the Application Heartbeats to assess performance goals and to inspect application progress and the Implementation Switch Service to switch between different implementations of the same algorithm (both in software and in hardware) at runtime. Preliminary results show the effectiveness and the usability of the proposed approach.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117102914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 41

High Density Asynchronous LUT Based on Non-volatile MRAM Technology 基于非易失性MRAM技术的高密度异步LUT

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.80

S. Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, C. Chappert, P. Mazoyer

引用次数: 4

Ultra-low-Power Ultra-fast Hybrid CNEMS-CMOS FPGA 超低功耗超高速混合CNEMS-CMOS FPGA

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.79

Vijay K. Sirigir, K. Alzoubi, D. Saab, F. Kocan, M. Tabib-Azar

{"title":"Ultra-low-Power Ultra-fast Hybrid CNEMS-CMOS FPGA","authors":"Vijay K. Sirigir, K. Alzoubi, D. Saab, F. Kocan, M. Tabib-Azar","doi":"10.1109/FPL.2010.79","DOIUrl":"https://doi.org/10.1109/FPL.2010.79","url":null,"abstract":"Energy efficiency and idle power consumption are becoming important parameters in the design of embedded systems that are realized with nanometer-scale CMOS devices. In nanometer-scale CMOS, Excessive quiescent power dissipation can lead to excessive heat generation and reliability issues. To address energy efficiency and idle power consumption, we present a novel Complementary Nano-Electro-Mechanical (CNEM) switch that we manufactured which operates with virtually zero leakage current, has 1 to 2 Volts operation voltage, $>$ 1 GHZ fundamental resonant frequency, and nanometer-scale footprint. These CNEM switches can be “dropped” in and hybridized with CMOS at the metallization or device levels to manage leakage current and power. In this paper, we present a hybrid CMOS/CNEMS FPGA. The hybrid FPGA is based on using the CNEM switching device as a replacement of CMOS devices in the switch and connection block components found in FPGA architectures. We analyzed the impact of the CNEM substitution on power and delay using VPR and the MCNC benchmark circuits. We present experimental results showing an average 98%, 85%, 71%, and 99.99% reduction in critical path delay, routing energy, total energy, leakage power when comparisons are made between FPGA design using pure CMOS (180nm technology and hybrid CNEMS and CMOS (180nm) technology.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125980968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Pipelined FPGA Adders 流水线FPGA加法器

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.87

F. D. Dinechin, Hong Diep Nguyen, B. Pasca

引用次数: 39

Rapid Application Development on Multi-processor Reconfigurable Systems 多处理器可重构系统的快速应用开发

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.65

Linfeng Ye, J. Diguet, G. Gogniat

引用次数: 11