2010 International Conference on Field Programmable Logic and Applications最新文献

Finding System-Level Information and Analyzing Its Correlation to FPGA Placement 寻找系统级信息并分析其与FPGA布局的相关性

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.107

Farnaz Gharibian, Lesley Shannon, P. Jamieson

{"title":"Finding System-Level Information and Analyzing Its Correlation to FPGA Placement","authors":"Farnaz Gharibian, Lesley Shannon, P. Jamieson","doi":"10.1109/FPL.2010.107","DOIUrl":"https://doi.org/10.1109/FPL.2010.107","url":null,"abstract":"One of the more popular placement algorithms for Field Programmable Gate Arrays (FPGAs) is called Simulated Annealing (SA). This algorithm tries to create a good quality placement from a flattened design that no longer contains any high-level information related to the original design hierarchy. Unfortunately, placement is an NP-hard problem and as the size and complexity of designs implemented on FPGAs increases, SA does not scale well to find good solutions in a timely fashion. As modern FPGAs can be used to implement Systems- and Networks-on-Chip, designers are required to spend an increasing amount of time waiting for place and route tools to complete that is not being matched by an increase in the power of computing work stations. In this paper, we investigate if system-level information can be reconstructed from a flattened netlist and evaluate how that information is realized in terms of its locality in the final placement. If there is a strong relationship between good quality placements and system-level information, then it may be possible to divide a large design into smaller components and improve the time needed to create a good quality placement. Our preliminary results suggest that the locality property of the information embedded in the system-level HDL structure (i.e. “module”, “always”, and “if” statements) is greatly affected by both the designer and the design itself. A reconstructive algorithm, called affinity propagation, is also considered as a possible method of generating a meaningful coarse grain picture of the design.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"26 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115510352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A Scalable, High-Performance Motion Estimation Application for a Weakly-Programmable FPGA Architecture 基于弱可编程FPGA架构的可扩展高性能运动估计应用

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.14

Henning Sahlbach, Sean Whitty, Oliver Bende, R. Ernst

{"title":"A Scalable, High-Performance Motion Estimation Application for a Weakly-Programmable FPGA Architecture","authors":"Henning Sahlbach, Sean Whitty, Oliver Bende, R. Ernst","doi":"10.1109/FPL.2010.14","DOIUrl":"https://doi.org/10.1109/FPL.2010.14","url":null,"abstract":"Computer architectures for advanced driver assistance systems have become increasingly important in the automotive industry. They target safety-critical applications, which process large amounts of incoming sensor data. This is especially the case for image processing applications, which must handle several uncompressed image streams from multiple cameras. As one possible target architecture, FPGAs provide sufficient processing power for complex applications such as lane or object detection. A particularly challenging application is the reliable detection of moving objects, which is the basis for several future driver assistance applications, such as a digital 3D reconstruction of a vehicle's surroundings. This paper presents an advanced Motion Estimation application, which achieves high performance processing of up to 449 FPS for an image resolution of 512x384 pixels. The implementation concept relies on weakly-programmable processing elements and a reconfigurable data path, which allows an efficient exploitation of the FPGA's chip area and clock frequencies, leading to a flexible solution that fits future application requirements.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114384853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

OpenRCL: Low-Power High-Performance Computing with Reconfigurable Devices OpenRCL:具有可重构设备的低功耗高性能计算

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.93

Mingjie Lin, Ilia A. Lebedev, J. Wawrzynek

{"title":"OpenRCL: Low-Power High-Performance Computing with Reconfigurable Devices","authors":"Mingjie Lin, Ilia A. Lebedev, J. Wawrzynek","doi":"10.1109/FPL.2010.93","DOIUrl":"https://doi.org/10.1109/FPL.2010.93","url":null,"abstract":"This work presents the Open Reconfigurable Computing Language (OpenRCL) system designed to enable low-power high-performance reconfigurable computing with imperative programming language such as C/C++. The key idea is to expose the FPGA platform as a compiler target for applications expressed in the OpenCL paradigm. To this end, we present a combination of low-level virtual machine instruction set, execution model, many-core architecture, and associated compiler to achieve high performance and power efficiency by exploiting the FPGA’s distributed memories and abundant hardware structures (such as DSP blocks, long carry-chains, and registers). Our resulting OpenRCL system not only allows programmers to easily express parallelism through the API defined in the OpenCL standard but also supports coarse-grain multithreading and dataflow-style fine-grain threading while permitting bit-level resource control. An OpenRCL prototype machine with 30 processing nodes was implemented using a Virtex-5 (XCV5LX155T-2) FPGA. For the well-known Parallel Prefix Sum (Scan) problem, comparing the runtime of the same problem on a GeForce 9400m using the OpenCL SDK from Apple Inc., the OpenRCL machine demonstrates comparable performance with a 5x reduction in core power consumption.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121879275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 44

A Flexible Compute and Memory Infrastructure for High-Level Language to Hardware Compilation 面向高级语言到硬件编译的灵活计算和内存基础结构

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.96

Hagen Gädke-Lütjens, Benjamin Thielmann, A. Koch

引用次数: 22

A Compact Transactional Memory Multiprocessor System on FPGA 基于FPGA的紧凑事务性存储器多处理器系统

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.113

Matteo Pusceddu, Simone Ceccolini, G. Palermo, D. Sciuto, Antonino Tumeo

引用次数: 6

On Identifying Patterns in Code Repositories to Assist the Generation of Hardware Templates 识别代码库中的模式以辅助硬件模板的生成

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.62

Adriano K. Sanches, João MP Cardoso

{"title":"On Identifying Patterns in Code Repositories to Assist the Generation of Hardware Templates","authors":"Adriano K. Sanches, João MP Cardoso","doi":"10.1109/FPL.2010.62","DOIUrl":"https://doi.org/10.1109/FPL.2010.62","url":null,"abstract":"The identification of patterns on large repositories of code can be of paramount importance to guide the design of new hardware accelerators, to acquire the suitability of a certain hardware accelerator, and to generate application-specific architectures that maximize hardware reuse. This work intends to research and develop methods to both acquire the presence of a given pattern (map-suitability) and to identify common and highly similar patterns in code repositories (design-suggestions). The approach being proposed is based on a number of identification layers that refine the selections at each stage. We analyze two possible complementary options for a high-level layer. A first option is based on the representation of programs as a sequence of symbols and string matching and clustering algorithms are then used to expose similar patterns. A second option is based on tree matching techniques for identifying the presence of user’s input patterns in the programs under inspection. We are evaluating our approach using the MiBench, MediaBench, UTDSP, and SNU code repositories. The results show the potential of our approach to identify approximate patterns that can be implemented by merging highly similar structures.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126528454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Exploiting Architectural Similarities and Mode Sequencing in Joint Cost Optimization of Multi-mode FIR Filters 多模FIR滤波器联合成本优化中的结构相似性和模式排序

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.42

A. H. Gholamipour, F. Kurdahi, A. Eltawil, M. Saghir

引用次数: 1

Sum of Absolute Difference Implementations for Image Processing on FPGAs fpga图像处理的绝对差分实现和

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.40

H. Niitsuma, T. Maruyama

引用次数: 15

Optimization of Regular Expression Pattern Matching Circuit Using At-Most Two-Hot Encoding on FPGA 在FPGA上使用最多双热编码优化正则表达式模式匹配电路

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.19

SangKyun Yun, KyuHee Lee

引用次数: 15

Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs 用于灵活多媒体sopc的运行时可扩展收缩协处理器

2010 International Conference on Field Programmable Logic and Applications Pub Date : 2010-08-31 DOI: 10.1109/FPL.2010.24

A. Otero, E. D. L. Torre, T. Riesgo, Y. Krasteva

{"title":"Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs","authors":"A. Otero, E. D. L. Torre, T. Riesgo, Y. Krasteva","doi":"10.1109/FPL.2010.24","DOIUrl":"https://doi.org/10.1109/FPL.2010.24","url":null,"abstract":"Multimedia Systems on Chip have high computational requirements, as well as significant flexibility demands. Flexibility can be related with the reusability of the cores in charge of the execution of computation-intensive tasks, but also with the run-time adaptation of these cores to the execution of time-variable tasks, or to changing system conditions. Among the run-time flexibility requirements of hardware IPs, functional scalability has been identified as an interesting feature. The proposal in this paper is to take advantage of the regularity and the high-processing capability of systolic arrays, to develop run-time functional scalable cores, making use of spatial scalability, by means of replicating and relocating basic processing elements of the array. The relocation process is performed using the dynamic-reconfiguration possibilities offered by commercial FPGAs. In this paper, an architectural template is proposed to develop systolic scalable coprocessors following this approach, together with its corresponding software drivers that may be executed within an embedded processor. In addition, a design flow is proposed to adapt the architectural template to different problems, together with some examples of scalable cores created following this design. This solution provides better results, regarding the reconfiguration time and the memory necessity overhead, compared with other dynamically scalable solutions.","PeriodicalId":171235,"journal":{"name":"2010 International Conference on Field Programmable Logic and Applications","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130915992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8