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1T DRAM with Raised SiGe Quantum Well for Sensing Margin Improvement 提高SiGe量子阱的1T DRAM传感裕度改善
IF 0.4 4区 工程技术
Journal of Semiconductor Technology and Science Pub Date : 2023-02-28 DOI: 10.5573/jsts.2023.23.1.64
Si-Won Lee, Seongjae Cho, I. Cho, Garam Kim
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引用次数: 0
Feasibility Study of Monitoring of Particle Generation in Plasma Etching Process by Plasma Impedance Measurement 等离子体阻抗测量监测等离子体蚀刻过程中粒子生成的可行性研究
IF 0.4 4区 工程技术
Journal of Semiconductor Technology and Science Pub Date : 2023-02-28 DOI: 10.5573/jsts.2023.23.1.50
Y. Kasashima, T. Tabaru, T. Ikeda
{"title":"Feasibility Study of Monitoring of Particle Generation in Plasma Etching Process by Plasma Impedance Measurement","authors":"Y. Kasashima, T. Tabaru, T. Ikeda","doi":"10.5573/jsts.2023.23.1.50","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.1.50","url":null,"abstract":"","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":"33 1","pages":""},"PeriodicalIF":0.4,"publicationDate":"2023-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75290192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Effects of Oxygen Content on Output Characteristics of IGZO TFTs under High Current Driving Conditions 氧含量对高电流驱动下IGZO TFTs输出特性的影响
IF 0.4 4区 工程技术
Journal of Semiconductor Technology and Science Pub Date : 2023-02-28 DOI: 10.5573/jsts.2023.23.1.71
Chae-Eun Oh, H. Kwon, Hwan-Seok Jeong, Su-Hyeon Lee, Dong-Ho Lee, Yeongkyun Kim, Myeong-Ho Kim, K. Son, Jun-Hyung Lim, Sang-Hun Song
{"title":"Effects of Oxygen Content on Output Characteristics of IGZO TFTs under High Current Driving Conditions","authors":"Chae-Eun Oh, H. Kwon, Hwan-Seok Jeong, Su-Hyeon Lee, Dong-Ho Lee, Yeongkyun Kim, Myeong-Ho Kim, K. Son, Jun-Hyung Lim, Sang-Hun Song","doi":"10.5573/jsts.2023.23.1.71","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.1.71","url":null,"abstract":"","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":"1 1","pages":""},"PeriodicalIF":0.4,"publicationDate":"2023-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89272714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Quantitative Analysis of Channel Width Effects on Electrical Performance Degradation of Top-gate Self-aligned Coplanar IGZO Thin-film Transistors under Self-heating Stresses 自热应力下沟道宽度对顶栅自对准共面IGZO薄膜晶体管电性能退化影响的定量分析
IF 0.4 4区 工程技术
Journal of Semiconductor Technology and Science Pub Date : 2023-02-28 DOI: 10.5573/jsts.2023.23.1.79
Dong-Ho Lee, Hwan-Seok Jeong, Yeongkyun Kim, Myeong-Ho Kim, K. Son, J. Lim, Sang-Hun Song, H. Kwon
{"title":"Quantitative Analysis of Channel Width Effects on Electrical Performance Degradation of Top-gate Self-aligned Coplanar IGZO Thin-film Transistors under Self-heating Stresses","authors":"Dong-Ho Lee, Hwan-Seok Jeong, Yeongkyun Kim, Myeong-Ho Kim, K. Son, J. Lim, Sang-Hun Song, H. Kwon","doi":"10.5573/jsts.2023.23.1.79","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.1.79","url":null,"abstract":"","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":"31 1","pages":""},"PeriodicalIF":0.4,"publicationDate":"2023-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81785451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Spread Spectrum Clock Generator with Dual-tone Hershey-Kiss Modulation Profile 一种双音Hershey-Kiss调制的扩频时钟发生器
IF 0.4 4区 工程技术
Journal of Semiconductor Technology and Science Pub Date : 2023-02-28 DOI: 10.5573/jsts.2023.23.1.39
Seong-Geun Kim, Taek-Joon An, Yongwoo Kim, Jinlong Kang
{"title":"A Spread Spectrum Clock Generator with Dual-tone Hershey-Kiss Modulation Profile","authors":"Seong-Geun Kim, Taek-Joon An, Yongwoo Kim, Jinlong Kang","doi":"10.5573/jsts.2023.23.1.39","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.1.39","url":null,"abstract":"","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":"33 1","pages":""},"PeriodicalIF":0.4,"publicationDate":"2023-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75244735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Shrink Generator-based Strong PUF Architecture with Improved Uniqueness and Reliability on an FPGA 基于收缩发生器的强PUF结构，提高了FPGA的唯一性和可靠性
IF 0.4 4区 工程技术
Journal of Semiconductor Technology and Science Pub Date : 2023-02-28 DOI: 10.5573/jsts.2023.23.1.26
Guard Kanda, K. Ryoo
{"title":"Shrink Generator-based Strong PUF Architecture with Improved Uniqueness and Reliability on an FPGA","authors":"Guard Kanda, K. Ryoo","doi":"10.5573/jsts.2023.23.1.26","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.1.26","url":null,"abstract":"","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":"14 1","pages":""},"PeriodicalIF":0.4,"publicationDate":"2023-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75145855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of Multiple Fin-type Vertical GaN Power Transistors based on Bulk GaN Substrates 基于大块GaN衬底的多翅片型垂直GaN功率晶体管分析
IF 0.4 4区 工程技术
Journal of Semiconductor Technology and Science Pub Date : 2023-02-28 DOI: 10.5573/jsts.2023.23.1.17
J. Heo, I. Kang, Sang-Ho Lee, Jin Park, S. Min, G. Kim, G. Kang, Jaewon Jang, J. Bae, Sin‐Hyung Lee
{"title":"Analysis of Multiple Fin-type Vertical GaN Power Transistors based on Bulk GaN Substrates","authors":"J. Heo, I. Kang, Sang-Ho Lee, Jin Park, S. Min, G. Kim, G. Kang, Jaewon Jang, J. Bae, Sin‐Hyung Lee","doi":"10.5573/jsts.2023.23.1.17","DOIUrl":"https://doi.org/10.5573/jsts.2023.23.1.17","url":null,"abstract":"","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":"77 1","pages":""},"PeriodicalIF":0.4,"publicationDate":"2023-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87091969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Study on Low-jitter and Low-power PLL Architectures for Mobile Audio Systems 移动音频系统低抖动低功耗锁相环架构研究
IF 0.4 4区 工程技术
Journal of Semiconductor Technology and Science Pub Date : 2022-12-31 DOI: 10.5573/jsts.2022.22.6.482
Yujin Kyung, G. Kim, Dong-Chul Baek
{"title":"Study on Low-jitter and Low-power PLL Architectures for Mobile Audio Systems","authors":"Yujin Kyung, G. Kim, Dong-Chul Baek","doi":"10.5573/jsts.2022.22.6.482","DOIUrl":"https://doi.org/10.5573/jsts.2022.22.6.482","url":null,"abstract":"","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":"23 3","pages":""},"PeriodicalIF":0.4,"publicationDate":"2022-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72626907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS Dual-mode DC-DC Converter with a Digital Dual-mode Controller 带有数字双模控制器的CMOS双模DC-DC变换器
IF 0.4 4区 工程技术
Journal of Semiconductor Technology and Science Pub Date : 2022-12-31 DOI: 10.5573/jsts.2022.22.6.426
K. Yoon, Jong-Whan Lee
{"title":"A CMOS Dual-mode DC-DC Converter with a Digital Dual-mode Controller","authors":"K. Yoon, Jong-Whan Lee","doi":"10.5573/jsts.2022.22.6.426","DOIUrl":"https://doi.org/10.5573/jsts.2022.22.6.426","url":null,"abstract":"","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":"58 1","pages":""},"PeriodicalIF":0.4,"publicationDate":"2022-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86575415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi-gate BCAT Structure and Select Word-line Driver in DRAM for Reduction of GIDL 多栅极BCAT结构和选择字行驱动的DRAM减少GIDL
IF 0.4 4区 工程技术
Journal of Semiconductor Technology and Science Pub Date : 2022-12-31 DOI: 10.5573/jsts.2022.22.6.452
Chang-Young Lim, M. Kwon
{"title":"Multi-gate BCAT Structure and Select Word-line Driver in DRAM for Reduction of GIDL","authors":"Chang-Young Lim, M. Kwon","doi":"10.5573/jsts.2022.22.6.452","DOIUrl":"https://doi.org/10.5573/jsts.2022.22.6.452","url":null,"abstract":"","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":"348 1","pages":""},"PeriodicalIF":0.4,"publicationDate":"2022-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73934288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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