发布求助
文献互助 智能选刊 最新文献

1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)最新文献

筛选
英文 中文
A systematic approach to the design of structures for arithmetic 一种系统的算法结构设计方法
1981 IEEE 5th Symposium on Computer Arithmetic (ARITH) Pub Date : 1981-05-16 DOI: 10.1109/ARITH.1981.6159291
J. E. Robertson
{"title":"A systematic approach to the design of structures for arithmetic","authors":"J. E. Robertson","doi":"10.1109/ARITH.1981.6159291","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159291","url":null,"abstract":"A design tool for the decomposition of binary digital structures for addition and subtraction has been developed. A simplified theory reduces a complex structure to a collection of basic structures of one type, namely, a full adder. The simplified theory is applicable to the design of parallel counters and array multipliers. A general theory is used for decomposition to three types of basic structures, whose complexity is usually on the order of a half-adder. The general theory is applicable to redundant array multipliers and signed-digit adders.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114068272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Arithmetic of finite fields 有限域的算法
1981 IEEE 5th Symposium on Computer Arithmetic (ARITH) Pub Date : 1981-05-16 DOI: 10.1109/ARITH.1981.6159289
T. Rao
{"title":"Arithmetic of finite fields","authors":"T. Rao","doi":"10.1109/ARITH.1981.6159289","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159289","url":null,"abstract":"The arithmetic operations in finite fields and their implementation are important to the construction of error detecting and correcting codes. The addition, multiplication and division in the field GF(2m) are implemented as polynomial operations using binary logic of flip-flops and EXOR's. For fields of non-binary characteristic, modular arithmetic (with modulus p, a prime) becomes important. This paper focuses on problems relating to the arithmetic of GF(p), and some recent results and new ideas on this topic are presented here.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124190252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Floating-point on-line arithmetic: Error analysis 浮点联机算术:误差分析
1981 IEEE 5th Symposium on Computer Arithmetic (ARITH) Pub Date : 1981-05-16 DOI: 10.1109/ARITH.1981.6159297
O. Watanuki, M. Ercegovac
{"title":"Floating-point on-line arithmetic: Error analysis","authors":"O. Watanuki, M. Ercegovac","doi":"10.1109/ARITH.1981.6159297","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159297","url":null,"abstract":"The properties of redundant number system in mantissa representation are studied and the range of the redundant mantissa is derived. From the range of the mantissa and the absolute error of on-line operations, the MRRE (maximum relative representation error) is defined and analyzed for redundant floating-point numbers.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130214757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A fast multi-operand multiplication scheme 一个快速的多操作数乘法方案
1981 IEEE 5th Symposium on Computer Arithmetic (ARITH) Pub Date : 1981-05-16 DOI: 10.1109/ARITH.1981.6159279
Hideaki Kobayashi
{"title":"A fast multi-operand multiplication scheme","authors":"Hideaki Kobayashi","doi":"10.1109/ARITH.1981.6159279","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159279","url":null,"abstract":"Recent developments in integrated circuit technology have made efficient schemes for computer arithmetic possible. This paper discusses a generation-summation scheme for fast multi-operand multiplication. Synthesis of three-operand multipliers utilizing a single type of standard LSI device is also discussed.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130861786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A rational arithmetic processor 理性算术处理机
1981 IEEE 5th Symposium on Computer Arithmetic (ARITH) Pub Date : 1981-05-16 DOI: 10.1109/ARITH.1981.6159277
M. J. Irwin, Dwight R. Smith
{"title":"A rational arithmetic processor","authors":"M. J. Irwin, Dwight R. Smith","doi":"10.1109/ARITH.1981.6159277","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159277","url":null,"abstract":"An arithmetic processor based upon a rational representation scheme is examined. The key feature of this rational processor is its ability to efficiently reduce a result ratio to its irreducible form (the greatest common divisor of the numerator and denominator is unity). The reduction algorithm presented generates the reduced ratio in parallel with the evaluation of the ratio's greatest common divisor. Hardware designs for the reduction algorithm and the basic arithmetic operations are given.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133325104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Compound algorithms for digit online arithmetic 数字在线算法的复合算法
1981 IEEE 5th Symposium on Computer Arithmetic (ARITH) Pub Date : 1981-05-16 DOI: 10.1109/ARITH.1981.6159285
R. Owens
{"title":"Compound algorithms for digit online arithmetic","authors":"R. Owens","doi":"10.1109/ARITH.1981.6159285","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159285","url":null,"abstract":"This paper describes a systematic method which has been successfully used to create several digit online algorithms. Basically, the method entails converting in a systematic way a known continued sums/products algorithm and combining the converted form of the continued sums/product algorithm with a generalized digitization algorithm. Not only does the method seem to have wide applicability in the creation of digit online algorithms for many elementary functions but the algorithms which have resulted from this method themselves have several desirable properties.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114392252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Partitioned algorithms and VLSI structures for large-scale matrix computations 大规模矩阵计算的划分算法和VLSI结构
1981 IEEE 5th Symposium on Computer Arithmetic (ARITH) Pub Date : 1981-05-16 DOI: 10.1109/ARITH.1981.6159276
K. Hwang, Yeng-Heng Cheng
{"title":"Partitioned algorithms and VLSI structures for large-scale matrix computations","authors":"K. Hwang, Yeng-Heng Cheng","doi":"10.1109/ARITH.1981.6159276","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159276","url":null,"abstract":"VLSI modular arithmetic structures and new partitioned matrix algorithms are developed in this paper to perform hardware matrix computations in solving large-scale linear system of equations. Gaussian elimination and inversion of triangular matrices are shown systematically partitionable. All the partitioned algorithms being developed can achieve linear computation time 0(n), where n is the order of the linear system. The partitioned matrix computations are feasible for modular VLSI implementation with constrained I/O terminals. Performance analysis and design tradeoffs of the partitioned VLSI arithmetic structures are also provided.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128731419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
High bandwidth evaluation of elementary functions 初等函数的高带宽评估
1981 IEEE 5th Symposium on Computer Arithmetic (ARITH) Pub Date : 1981-05-16 DOI: 10.1109/ARITH.1981.6159271
P. Farmwald
{"title":"High bandwidth evaluation of elementary functions","authors":"P. Farmwald","doi":"10.1109/ARITH.1981.6159271","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159271","url":null,"abstract":"Among the requirements currently being imposed on high-performance digital computers to an increasing extent are the high-bandwidth computations of elementary functions, which are relatively time-consuming procedures when conducted in software. In this paper, we elaborate on a technique for computing piecewise quadratric approximations to many elementary functions. This method permits the effective use of large RAMs or ROMs and parallel multipliers for rapidly generating single-precision floating-point function values (e.g., 30–45 bits of fraction, with current RAM and ROM technology). The technique, based on the use of Taylor series, may be readily pipelined. Its use for calculating values for floating-point reciprocal, square root, sine, cosine, arctangent, logarithm, exponential and error functions is discussed.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134371600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
VAX hardware for the proposed IEEE floating-point standard VAX硬件为建议的IEEE浮点标准
1981 IEEE 5th Symposium on Computer Arithmetic (ARITH) Pub Date : 1981-05-16 DOI: 10.1109/ARITH.1981.6159294
G. Taylor, D. Patterson
{"title":"VAX hardware for the proposed IEEE floating-point standard","authors":"G. Taylor, D. Patterson","doi":"10.1109/ARITH.1981.6159294","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159294","url":null,"abstract":"The proposed IEEE floating-point standard has been implemented in a substitute floating-point accelerator for the VAX∗∗ 11/780. We explain how features of the proposed standard influenced the design of the new processor. By comparing it with the original VAX accelerator, we illustrate the differences between hardware for the proposed standard and hardware for a more traditional floating-point architecture.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123043338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A systematic approach to the design of structures for addition and subtraction — Case of radix r = mk 加减法结构设计的系统方法——基数r = mk的情况
1981 IEEE 5th Symposium on Computer Arithmetic (ARITH) Pub Date : 1981-05-16 DOI: 10.1109/ARITH.1981.6159283
D. Nguyen
{"title":"A systematic approach to the design of structures for addition and subtraction — Case of radix r = mk","authors":"D. Nguyen","doi":"10.1109/ARITH.1981.6159283","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159283","url":null,"abstract":"The results of Robertson concerning, a systematic approach to the design of Adder/Subtracter structures of radix r=2k, k ≥ I are generalised to cover all structures of radix r = mk, k ≥ I and m ≥ 2 The use of Quasi binary representations help reduce the number of types of fundamental structures required. In addition to the types encountered in the earlier case, only one new type of fundamental structures called Radix-m Carry Generator is needed. Examples in the particular case of Decimal Adder/Subtracter structures are used to illustrate the results.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114964863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信