VAX硬件为建议的IEEE浮点标准

G. Taylor, D. Patterson
{"title":"VAX硬件为建议的IEEE浮点标准","authors":"G. Taylor, D. Patterson","doi":"10.1109/ARITH.1981.6159294","DOIUrl":null,"url":null,"abstract":"The proposed IEEE floating-point standard has been implemented in a substitute floating-point accelerator for the VAX∗∗ 11/780. We explain how features of the proposed standard influenced the design of the new processor. By comparing it with the original VAX accelerator, we illustrate the differences between hardware for the proposed standard and hardware for a more traditional floating-point architecture.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"VAX hardware for the proposed IEEE floating-point standard\",\"authors\":\"G. Taylor, D. Patterson\",\"doi\":\"10.1109/ARITH.1981.6159294\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The proposed IEEE floating-point standard has been implemented in a substitute floating-point accelerator for the VAX∗∗ 11/780. We explain how features of the proposed standard influenced the design of the new processor. By comparing it with the original VAX accelerator, we illustrate the differences between hardware for the proposed standard and hardware for a more traditional floating-point architecture.\",\"PeriodicalId\":169426,\"journal\":{\"name\":\"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)\",\"volume\":\"107 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1981-05-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ARITH.1981.6159294\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARITH.1981.6159294","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8

摘要

提出的IEEE浮点标准已在VAX * * 11/780的替代浮点加速器中实现。我们将解释拟议标准的特性如何影响新处理器的设计。通过将其与原始的VAX加速器进行比较,我们说明了所提议标准的硬件与更传统的浮点体系结构的硬件之间的差异。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
VAX hardware for the proposed IEEE floating-point standard
The proposed IEEE floating-point standard has been implemented in a substitute floating-point accelerator for the VAX∗∗ 11/780. We explain how features of the proposed standard influenced the design of the new processor. By comparing it with the original VAX accelerator, we illustrate the differences between hardware for the proposed standard and hardware for a more traditional floating-point architecture.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信