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2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)最新文献

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Observation of current filaments in IGBTs with thermoreflectance microscopy 用热反射显微镜观察igbt电流细丝
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393628
Riteshkumar Bhojani, J. Kowalsky, J. Lutz, D. Kendig, R. Baburske, H. Schulze, F. Niedernostheide
{"title":"Observation of current filaments in IGBTs with thermoreflectance microscopy","authors":"Riteshkumar Bhojani, J. Kowalsky, J. Lutz, D. Kendig, R. Baburske, H. Schulze, F. Niedernostheide","doi":"10.1109/ISPSD.2018.8393628","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393628","url":null,"abstract":"In this paper, we demonstrate for the first time experimentally measured current filaments in IGBTs under repetitive Short-Circuit (SC) events. These current filaments were discovered with the help of Thermo-Reflectance Microscopy (TRM). The destruction current as function of the applied collector-emitter voltage (VCE) was determined for two differently wire-bonded 15A-1200V IGBT chips. The repetitive SC events in combination with TRM measurement indicate a wide range of non-destructive current filaments at different VCE. Similar filament formation under short-circuit conditions were observed in supporting TCAD device simulations based on multi-cell IGBT structure. These filaments have similar dimensions to the current filaments measured by TRM.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122260654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
IGBT structure with electrically separated floating-p region improving turn-on dVak/dt controllability 具有电分离浮动p区的IGBT结构，提高了导通dVak/dt的可控性
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393629
Y. Ikura, Y. Onozawa, A. Nakagawa
{"title":"IGBT structure with electrically separated floating-p region improving turn-on dVak/dt controllability","authors":"Y. Ikura, Y. Onozawa, A. Nakagawa","doi":"10.1109/ISPSD.2018.8393629","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393629","url":null,"abstract":"IGBT cell structure for improving the turn-on dIc/dt controllability is presented. The difference from the conventional structure is that the floating-p region of the new structure is electrically disconnected from the trench-side-wall region. TCAD simulation suggests that the new device structure achieves better turn-on characteristics and almost the same static and turn-off characteristics compared to the conventional structure. It turned out that the high potential of the trench-side-wall region of the new structure, at the moment just before the collector current start to flow, is the cause of the improved turn-on dIc/dt controllability.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115487438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Long term high temperature reverse bias (HTRB) test on high voltage SiC-JBS-diodes 高压sic - jbs二极管的长期高温反向偏置(HTRB)测试
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393696
F. Hoffmann, A. Mihaila, L. Kranz, P. Godignon, N. Kaminski
{"title":"Long term high temperature reverse bias (HTRB) test on high voltage SiC-JBS-diodes","authors":"F. Hoffmann, A. Mihaila, L. Kranz, P. Godignon, N. Kaminski","doi":"10.1109/ISPSD.2018.8393696","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393696","url":null,"abstract":"In this paper, the result of a long term HTRB Test with a test time over 5000 hours on novel 3.3kV SiC-JBS-Diodes is presented. The diodes under test have an area of 5×5mm2 with a p-stripe design and a JTE-based edge-termination. Two splits were tested, one with globtop cover underneath silicone gel potting and the other with gel potting only. Both splits show a significant decrease in leakage current over the course of the test. A different behavior of leakage current is observed when test conditions are reapplied after an interruption for intermediate measurements. It is evident that the leakage current is not only affected by the chip but also by the surrounding materials. Both splits passed over 5000 hours without failure.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115907468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A high-voltage p-LDMOS with enhanced current capability comparable to double RESURF n-LDMOS 一种具有增强电流能力的高压p-LDMOS，可与双RESURF n-LDMOS相媲美
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393624
B. Yi, Junji Cheng, M. Kong, Bingke Zhang, Xingbi Chen
{"title":"A high-voltage p-LDMOS with enhanced current capability comparable to double RESURF n-LDMOS","authors":"B. Yi, Junji Cheng, M. Kong, Bingke Zhang, Xingbi Chen","doi":"10.1109/ISPSD.2018.8393624","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393624","url":null,"abstract":"In this paper, a simple p-LDMOS structure with significantly improved performances based on a novel three dimensional concept is proposed. The hole current in the Ptop region of the signal region flows into the floating P+, then through the integrated resistor Rp formed by the Pbase region in the z-axis direction with a distance of W2+W3, into electrode D. A voltage drop (VGn) which controls the n-channel will be auto-generated across Rp during the on- and off-state of the hole current. Thus the p-LDMOS applies both hole and electron as majority carriers to conduct current. The proposed p-LDMOS, having only one external controlling signal (GP), has a current capability comparable to or even larger than that of an optimized double RESURF n-LDMOS implemented through the same process steps. The power loss can be reduced by 74.9% compared with the conventional p-LDMOS.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124395812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new 1200 V HVIC with high side edge trigger in order to solve the latch on failure by the negative VS surge 一个新的1200伏HVIC高侧边触发，以解决闩锁故障负VS浪涌
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393675
Ki-Nam Song, Wonhi Oh, Jinkyu Choi, S. Hong, Sangmin Park
{"title":"A new 1200 V HVIC with high side edge trigger in order to solve the latch on failure by the negative VS surge","authors":"Ki-Nam Song, Wonhi Oh, Jinkyu Choi, S. Hong, Sangmin Park","doi":"10.1109/ISPSD.2018.8393675","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393675","url":null,"abstract":"This paper investigates the root cause of the latch on failure by a short turn-on input signal with a negative VS surge and proposes a new 1200 V HVIC with a high side edge trigger in order to solve the latch on failure. The proposed HVIC is fabricated using a 1.2 μm 1200 V BCDMOS process. The experimental results show the latch on failure no longer occurs on the new 1200 V HVIC because it doesn't overlap the VS recovery period and the RESET pulse period. The proposed HVIC can be applied to IPM modules (intelligent power modules) and APM modules (automotive power modules) which require a more robust HVIC solution.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124542419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Short circuit robustness analysis of new generation Enhancement-mode p-GaN power HEMTs 新一代增强型p-GaN功率hemt的短路鲁棒性分析
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393613
M. Riccio, G. Romano, L. Maresca, G. Breglio, A. Irace, G. Longobardi
{"title":"Short circuit robustness analysis of new generation Enhancement-mode p-GaN power HEMTs","authors":"M. Riccio, G. Romano, L. Maresca, G. Breglio, A. Irace, G. Longobardi","doi":"10.1109/ISPSD.2018.8393613","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393613","url":null,"abstract":"This work discusses about the short-circuit capability of new generation Enhancement-mode p-GaN power HEMTs. The electrothermal behavior of two commercially available devices is experimentally verified up to the failure events. Mission profile compact thermal simulations are used to estimate temperature increase during short-circuit tests. The assumption of a temperature-dependent gate current is then investigated by means of 2D electro-thermal TCAD simulations on a reference structure. Finally, a possible trade-off between gate driver resistance and short-circuit capability is discussed.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124490101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
AC/DC flyback controller with UHV integrated startup current source in 180nm HVIC technology 交/直流反激控制器与特高压集成启动电流源在180nm HVIC技术
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393677
H. Kwan, B. Nguyen, Wen-Cheng Lin, Xiaoxin Liu, Swapnil Pandey, Sandip Chakraborty, Jongjib Kim, D. Disney
{"title":"AC/DC flyback controller with UHV integrated startup current source in 180nm HVIC technology","authors":"H. Kwan, B. Nguyen, Wen-Cheng Lin, Xiaoxin Liu, Swapnil Pandey, Sandip Chakraborty, Jongjib Kim, D. Disney","doi":"10.1109/ISPSD.2018.8393677","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393677","url":null,"abstract":"This work demonstrates an AC/DC flyback converter controller fabricated in an 180nm HVIC technology that enables reduced layout size and increased digital content. It features a monolithically integrated ultra-high-voltage (UHV) start-up circuit. An integrated UHV depletion-mode transistor is used to draw current directly from the ∼400V DC bus and charge up VDD to ∼13V. Controlling the gate of this depletion transistor allows the start-up current to be completely cut off after the VDD is charged and the controller starts normal operation, which cannot be done using the resistor start-up approach. The start-up circuit includes built-in protection features and enables tight tolerances for key design parameters.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126175415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
40 V to 100 V NLDMOS built on thin BOX SOI with high energy capability, state of the art Rdson/BVdss and robust performance 40 V至100 V NLDMOS基于薄盒SOI，具有高能量能力，最先进的Rdson/BVdss和强大的性能
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393708
Y. Hao, Sim Poh Ching, M. Liew, A. Hoelke, U. Eckoldt, M. Pfost
{"title":"40 V to 100 V NLDMOS built on thin BOX SOI with high energy capability, state of the art Rdson/BVdss and robust performance","authors":"Y. Hao, Sim Poh Ching, M. Liew, A. Hoelke, U. Eckoldt, M. Pfost","doi":"10.1109/ISPSD.2018.8393708","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393708","url":null,"abstract":"We report in this paper for the first time that power LDMOS transistors integrated in thin BOX SOI can achieve high energy capabilities comparable to bulk BCD technologies and almost identical breakdown voltages for both high and low side applications. With proper top silicon thickness consideration, NLDMOS transistors for a voltage range from 40V to 100V with state of the art Rdson/BVdss trade-off and robust device performance are successfully constructed via a simple design concept.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114141046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
High-speed, high-reliability GaN power device with integrated gate driver 具有集成栅极驱动器的高速、高可靠性GaN功率器件
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393606
Gaofei Tang, M. Kwan, Zhaofu Zhang, Jiabei He, Jiacheng Lei, R. Su, F. Yao, Y.-M. Lin, J.-L. Yu, Thomas Yang, Chan-Hong Chern, Tom Tsai, H. Tuan, A. Kalnitsky, K. J. Chen
{"title":"High-speed, high-reliability GaN power device with integrated gate driver","authors":"Gaofei Tang, M. Kwan, Zhaofu Zhang, Jiabei He, Jiacheng Lei, R. Su, F. Yao, Y.-M. Lin, J.-L. Yu, Thomas Yang, Chan-Hong Chern, Tom Tsai, H. Tuan, A. Kalnitsky, K. J. Chen","doi":"10.1109/ISPSD.2018.8393606","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393606","url":null,"abstract":"An enhancement-mode GaN power switch with monolithically integrated gate driver is demonstrated on a 650-V GaN-on-Si power device platform. The integrated GaN-based gate driver features advanced designs such as bootstrapped gate-charging current source that enables high current driving capability during the entire turn-on process and rail-to-rail output. The GaN power transistor with integrated gate driver was characterized up to 300 V/15 A switching operations using a double pulse tester, and exhibits suppressed gate ringing and fast switching speed. The peak drain voltage slew rate d V/dt is above 125 V/ns during turn-on, and 336 V/ns during turn-off.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131201108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 51
Effects of inorganic encapsulation on power cycling lifetime of aluminum bond wires 无机封装对铝结合线功率循环寿命的影响
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393648
Nan Jiang, M. Scheibel, Benjamin Fabian, Marko Kalajica, A. Miric, J. Lutz
{"title":"Effects of inorganic encapsulation on power cycling lifetime of aluminum bond wires","authors":"Nan Jiang, M. Scheibel, Benjamin Fabian, Marko Kalajica, A. Miric, J. Lutz","doi":"10.1109/ISPSD.2018.8393648","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393648","url":null,"abstract":"Bond wire lift-offs and heel cracks are regarded as one of the main failure mechanisms of the bond wires in the power modules. In previous studies, the reliability of the bond wires can be improved by applying encapsulations to cover the bond wires. In this work, the investigation was mainly focused on the effect of inorganic encapsulation on the reliability of the aluminum bond wires under the power cycling test. Samples with different encapsulation positions were tested in order to evaluate the dependency of the encapsulation position on the reliability of the bond stitches. The results of power cycling tests and shear tests showed a reliability improvement of the tested samples when the aluminum bond wires was covered by the inorganic encapsulation. Besides, the reliability improvement of the samples was highly related to the covered position of the bond stitches. Thermal-mechanical simulation results indicated the heel cracks had stronger influence on the encapsulated bond wires at the certain position than the other position, which may be the reason of the position dependency of the encapsulation on the reliability improvement of the bond wires.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115137961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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