2015 International Workshop on Computational Electronics (IWCE)最新文献_第3页

Strong negative differential resistance in graphene devices with local strain 具有局部应变的石墨烯器件的强负差分电阻

2015 International Workshop on Computational Electronics (IWCE) Pub Date : 2015-10-26 DOI: 10.1109/IWCE.2015.7301954

M. Nguyen, V. Nguyen, J. Saint-Martin, P. Dollfus

引用次数: 3

Nanosized-metal-grain-induced characteristic fluctuation in gate-all-around si nanowire metal-oxide-semiconductor devices 栅极全能硅纳米线金属氧化物半导体器件中纳米尺寸金属晶粒诱导的特性波动

2015 International Workshop on Computational Electronics (IWCE) Pub Date : 2015-10-26 DOI: 10.1109/IWCE.2015.7301971

C. Lai, Chien-Yang Chen, Yiming Li

引用次数: 2

Effect of confinement in III-V nanowire field effect transistors 约束对III-V纳米线场效应晶体管的影响

2015 International Workshop on Computational Electronics (IWCE) Pub Date : 2015-10-26 DOI: 10.1109/IWCE.2015.7301980

A. Price, A. Martinez

引用次数: 0

Multi-subband interface roughness scattering using 2D finite element schodinger equation for monte carlo simulations of multi-gate transistors 基于二维有限元schodinger方程的多栅极晶体管多子带界面粗糙度散射蒙特卡罗模拟

2015 International Workshop on Computational Electronics (IWCE) Pub Date : 2015-10-26 DOI: 10.1109/IWCE.2015.7301977

D. Nagy, M. Elmessary, M. Aldegunde, J. Lindberg, A. García-Loureiro, K. Kalna

引用次数: 1

Reformulation of quantum noise: when indistinguishable becomes distinguishable? 量子噪声的重新表述:当不可区分变成可区分?

2015 International Workshop on Computational Electronics (IWCE) Pub Date : 2015-10-26 DOI: 10.1109/IWCE.2015.7301949

E. Colomés, D. Marian, X. Oriols

引用次数: 0

Strain effects on the electronic properties of devices made of twisted graphene layers 应变对扭曲石墨烯层器件电子性能的影响

2015 International Workshop on Computational Electronics (IWCE) Pub Date : 2015-10-26 DOI: 10.1109/IWCE.2015.7301952

V. Nguyen, J. Saint-Martin, P. Dollfus, Huy V. Nguyen

引用次数: 0

Self-consistent physical modeling of SiOx-based RRAM structures 基于siox的RRAM结构自洽物理建模

2015 International Workshop on Computational Electronics (IWCE) Pub Date : 2015-10-26 DOI: 10.1109/IWCE.2015.7301981

T. Sadi, Liping Wang, L. Gerrer, V. Georgiev, A. Asenov

引用次数: 4

Modeling polycrystalline effects on the device characteristics of cdte based solar cells 多晶对cdte基太阳能电池器件特性的影响

2015 International Workshop on Computational Electronics (IWCE) Pub Date : 2015-10-26 DOI: 10.1109/IWCE.2015.7301976

Souvik Mukherjee, S. Farid, M. Stroscio, M. Dutta

{"title":"Modeling polycrystalline effects on the device characteristics of cdte based solar cells","authors":"Souvik Mukherjee, S. Farid, M. Stroscio, M. Dutta","doi":"10.1109/IWCE.2015.7301976","DOIUrl":"https://doi.org/10.1109/IWCE.2015.7301976","url":null,"abstract":"There are mainly three different types of losses that accounts for the decrease in the efficiency of polycrystalline CdTe solar cells namely: (1) optical losses resulting from the interface reflections and absorption from the window and buffer layers in superstrate configuration; (2) recombination losses due to the interface between adjacent layers and also at grain boundaries; and (3) electrical losses due to the device series and shunt resistances. Over the years researchers have mostly studied the nature of the optical and electrical losses in single crystalline cells and have put forward various theoretical models to accurately explain their effect on various performance parameters. However the problem gets much complicated for polycrystalline materials as grain size effects can significantly affect these performance parameters such as short circuit current, open circuit voltage and fill factor. In this work we have studied these polycrystalline effects in depth and have presented a comparative analysis using minority carrier lifetime based model to accurately formulate micron scale grain size effects in CdTe based solar cells.","PeriodicalId":165023,"journal":{"name":"2015 International Workshop on Computational Electronics (IWCE)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134450866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Screening effect on electric field produced by spontaneous polarization in ZnO quantum dot in electrolyte 电解质中ZnO量子点自发极化产生电场的屏蔽效应

2015 International Workshop on Computational Electronics (IWCE) Pub Date : 2015-10-26 DOI: 10.1109/IWCE.2015.7301943

M. S. Choi, X. Meshik, M. Dutta, M. Stroscio

引用次数: 3

Progress on quantum transport simulation using empirical pseudopotentials 基于经验赝势的量子输运模拟研究进展

2015 International Workshop on Computational Electronics (IWCE) Pub Date : 2015-10-26 DOI: 10.1109/IWCE.2015.7301957

Jingtian Fang, W. Vandenberghe, M. Fischetti

{"title":"Progress on quantum transport simulation using empirical pseudopotentials","authors":"Jingtian Fang, W. Vandenberghe, M. Fischetti","doi":"10.1109/IWCE.2015.7301957","DOIUrl":"https://doi.org/10.1109/IWCE.2015.7301957","url":null,"abstract":"After performing one-dimensional simulation of electron transport in narrow quantum wires without gate control in (Fang et al., 2014) and (Fu and Fischetti, 2013) using the open boundary-conditions full-band plane-wave transport formalism derived in (Fu, 2013), we now extend the work to simulate three-dimensionally field-effect transistors (FETs) with a gate bias applied and obtain their transport characteristics. We optimize multiple procedures for solving the quantum transport equation (QTE), such as using a selected eigenvalue solver, the fast Fourier transform (FFT), block assignment of matrices, a sparse matrix solver, and parallel computing techniques. With an expanded computing capability, we are able to simulate the transistors in the sub- 1 nm technology node as suggested by the ITRS, which features 5 nm physical gate length, 2 nm body thick6ness, 0.4 nm effective oxide thickness (EOT), 0.6 V power supply voltage, and a multi-gate structure. Here we simulate an armchair graphene nanoribbon (aGNR) FET using a gateall- around architecture and obtain its transport properties. We will discuss the numerics concerning the matrix size of the transport equation, memory consumption, and simulation time.","PeriodicalId":165023,"journal":{"name":"2015 International Workshop on Computational Electronics (IWCE)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116380183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1