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Toroidal versus spiral inductors in multilayered technologies 多层技术中的环形与螺旋电感
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2016-05-22 DOI: 10.1109/RFIC.2016.7508249
J. López-Villegas, N. Vidal, J. D. del Alamo
{"title":"Toroidal versus spiral inductors in multilayered technologies","authors":"J. López-Villegas, N. Vidal, J. D. del Alamo","doi":"10.1109/RFIC.2016.7508249","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508249","url":null,"abstract":"This work is aimed to compare the performance of toroidal inductors and planar spiral inductors in multi-layered technologies. Toroidal inductors are investigated theoretically, and closed formula is derived for the inductance as a function of geometrical parameters. The obtained model is validated by experimental results and EM simulation. From the comparison of the inductance of toroidal inductors and compact spiral inductors, a selection rule is proposed to choose the most suitable topology that leads to the most compact design.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117229204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 60GHz packaged switched beam 32nm CMOS TRX with broad spatial coverage, 17.1dBm peak EIRP, 6.1dB NF at < 250mW 60GHz封装开关波束32nm CMOS TRX具有宽空间覆盖，17.1dBm峰值EIRP， < 250mW时6.1dB NF
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2016-05-22 DOI: 10.1109/RFIC.2016.7508322
B. Sadhu, A. Valdes-Garcia, J. Plouchart, H. Ainspan, A. Gupta, M. Ferriss, M. Yeck, M. Sanduleanu, X. Gu, C. Baks, D. Liu, D. Friedman
{"title":"A 60GHz packaged switched beam 32nm CMOS TRX with broad spatial coverage, 17.1dBm peak EIRP, 6.1dB NF at < 250mW","authors":"B. Sadhu, A. Valdes-Garcia, J. Plouchart, H. Ainspan, A. Gupta, M. Ferriss, M. Yeck, M. Sanduleanu, X. Gu, C. Baks, D. Liu, D. Friedman","doi":"10.1109/RFIC.2016.7508322","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508322","url":null,"abstract":"A low power, small form-factor, 60-GHz radio with beam switching capability is presented. The 3mm×3mm radio IC in 32nm SOI CMOS includes the TX and RX RF front ends, mixers, basebands, PLL and LO chains. The package comprises 2 TX antennas and 2 RX antennas producing low directivity beams in two orthogonal directions to maximize spatial coverage, with an achieved angular coverage of 254°. In board level measurements of the half duplex packaged radio, 17.1dBm EIRP and 6.1dB noise figure are achieved, with power consumption below 250mW.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"2007 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125841559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An efficient 210GHz compact harmonic oscillator with 1.4dBm peak output power and 10.6% tuning range in 130nm BiCMOS 一个高效的210GHz紧凑谐振子，峰值输出功率为1.4dBm，调谐范围为10.6%
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2016-05-22 DOI: 10.1109/RFIC.2016.7508284
Chen Jiang, A. Cathelin, E. Afshari
{"title":"An efficient 210GHz compact harmonic oscillator with 1.4dBm peak output power and 10.6% tuning range in 130nm BiCMOS","authors":"Chen Jiang, A. Cathelin, E. Afshari","doi":"10.1109/RFIC.2016.7508284","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508284","url":null,"abstract":"A compact 210GHz harmonic oscillator is presented. By utilizing a device-centric bottom-up design methodology as well as the return-path gap coupler and self-feeding structure, the harmonic power generation is optimized. Fabricated with a 130nm SiGe BiCMOS process, the oscillator core occupies only 290×95 μm2 area. It achieves a 1.4dBm peak output power and 2.4% peak DC-to-RF efficiency. The output frequency can be tuned from 197.5GHz to 219.7GHz. The phase noise is measured to be -87.5dBc/Hz at 1MHz offset.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124693861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
A direct-conversion receiver for multi-carrier 3G/4G small-cell base stations in 65nm CMOS 用于多载波3G/4G小蜂窝基站的65nm CMOS直接转换接收器
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2016-05-22 DOI: 10.1109/RFIC.2016.7508253
David J. McLaurin, K. Gard, Richard P. Schubert, Robert Glenn, D. Alldred, T. Caldwell, Z. Li, Steve Bal, C. Angell, Jianxun Fan, M. Manglani, Brian Reggiannini, J. Kornblum, Lu Wu, Chris Mayer, Oliver E. Gysel, W. An, S. Bhal, Bruce E. Wilcox, T. Montalvo
{"title":"A direct-conversion receiver for multi-carrier 3G/4G small-cell base stations in 65nm CMOS","authors":"David J. McLaurin, K. Gard, Richard P. Schubert, Robert Glenn, D. Alldred, T. Caldwell, Z. Li, Steve Bal, C. Angell, Jianxun Fan, M. Manglani, Brian Reggiannini, J. Kornblum, Lu Wu, Chris Mayer, Oliver E. Gysel, W. An, S. Bhal, Bruce E. Wilcox, T. Montalvo","doi":"10.1109/RFIC.2016.7508253","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508253","url":null,"abstract":"We present a 65nm direct conversion receiver for small cell 3G/4G basestations. The receiver supports up to 100MHz of RF BW and carrier frequencies from 400MHz to 6GHz, with 80dB image rejection and 76dB in-band SFDR. The direct conversion architecture eliminates IF filtering and the need for RF filtering of images and M×N mixing products, reducing basestation size and cost.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123738564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An RF-powered 58Mbps-TX 2.5Mbps-RX full-duplex transceiver for neural microimplants 用于神经微植入物的射频供电58Mbps-TX 2.5Mbps-RX全双工收发器
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2016-05-22 DOI: 10.1109/RFIC.2016.7508294
Yashar Rajavi, M. Taghivand, Kamal Aggarwal, Andrew Ma, A. Poon
{"title":"An RF-powered 58Mbps-TX 2.5Mbps-RX full-duplex transceiver for neural microimplants","authors":"Yashar Rajavi, M. Taghivand, Kamal Aggarwal, Andrew Ma, A. Poon","doi":"10.1109/RFIC.2016.7508294","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508294","url":null,"abstract":"A wirelessly-powered, high-data-rate transceiver for neuro-modulation applications is presented. The transceiver achieves 58Mbps in TX, and 2.5Mbps in RX. It enables bidirectional full-duplex communication using an external duplexer. The TX operates at 1.74GHz and consumes 93μW, while the RX operates at 1.86GHz and consumes 7.2μW. The prototype was fabricated in 40nm LP CMOS and occupies 0.8mm2. The overall system size including the duplexer is 3.2mm2.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127881331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 93.4-to-104.8 GHz 57 mW fractional-N cascaded sub-sampling PLL with true in-phase injection-coupled QVCO in 65 nm CMOS 一种93.4- 104.8 GHz 57 mW分数n级联子采样锁相环，具有真正的同相注入耦合QVCO
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2016-05-22 DOI: 10.1109/RFIC.2016.7508266
Xiang Yi, Zhipeng Liang, Guangyin Feng, C. Boon, F. Meng
{"title":"A 93.4-to-104.8 GHz 57 mW fractional-N cascaded sub-sampling PLL with true in-phase injection-coupled QVCO in 65 nm CMOS","authors":"Xiang Yi, Zhipeng Liang, Guangyin Feng, C. Boon, F. Meng","doi":"10.1109/RFIC.2016.7508266","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508266","url":null,"abstract":"A fully integrated 93.4-to-104.8 GHz 57 mW cascaded PLL, with true in-phase injection-coupled QVCO, occupies 0.88 mm2 in 65 nm CMOS. By cascading the fractional-N PLL and the sub-sampling PLL, good phase noise, high resolution and wide acquisition range are achieved simultaneously. The measured phase noise of QVCO and PLL are -112.67 and -108.75 dBc/Hz at 10 MHz offset, respectively. The FOM and FOMT of the QVCO at 10 MHz offset are -177.5 and -179.0 dBc/Hz, respectively.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129173325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 130-nm SOI CMOS reconfigurable multimode multiband power amplifier for 2G/3G/4G handset applications 一款用于2G/3G/4G手机应用的130纳米SOI CMOS可重构多模多带功率放大器
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2016-05-22 DOI: 10.1109/RFIC.2016.7508299
P. Ferris, G. Tant, A. Giry, J. Arnould, J. Fournier
{"title":"A 130-nm SOI CMOS reconfigurable multimode multiband power amplifier for 2G/3G/4G handset applications","authors":"P. Ferris, G. Tant, A. Giry, J. Arnould, J. Fournier","doi":"10.1109/RFIC.2016.7508299","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508299","url":null,"abstract":"This paper presents a reconfigurable multimode multiband power amplifier (MMPA) integrated in a 130nm SOI CMOS technology. In 2G mode, a saturated output power of 34.6/35.5dBm with a corresponding power added efficiency (PAE) of 61/53% was measured at 800/900MHz. In 3G/4G mode, a linear output power higher than 28/27dBm with a PAE higher than 34/33% while keeping adjacent channel leakage power ratio (ACLR) less than -36/-33dBc was measured with WCDMA and LTE signals respectively in the 700-900MHz frequency range. At 900MHz, up to 39/37% PAE is achieved with WCDMA/LTE signals. Up to 15% boost in PAE was achieved at 700MHz and 900MHz by using reconfigurable matching network, which validates the usefulness of the proposed reconfigurable architecture. The fabricated circuit occupies an area of 2.9mm2. To our best knowledge, this 2-stage reconfigurable single-core MMPA is the first reported SOI LDMOS MMPA addressing 2G/3G/4G modes and covering an extended frequency range from 700MHz to 900MHz.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"2004 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116051158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 28GHz SiGe BiCMOS phase invariant VGA 一个28GHz SiGe BiCMOS相位不变VGA
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2016-05-22 DOI: 10.1109/RFIC.2016.7508273
B. Sadhu, J. Bulzacchelli, A. Valdes-Garcia
{"title":"A 28GHz SiGe BiCMOS phase invariant VGA","authors":"B. Sadhu, J. Bulzacchelli, A. Valdes-Garcia","doi":"10.1109/RFIC.2016.7508273","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508273","url":null,"abstract":"The paper describes a technique to design a phase invariant variable gain amplifier (VGA). Variable gain is achieved by varying the bias current in a BJT, while the phase variation is minimized by designing a local feedback network such that the applied base to emitter voltage has a bias-dependent phase variation which compensates the inherent phase variation of the transconductance. Two differential 28GHz VGA variants based on these principles achieve <;5° phase variation over 8dB and 18dB of gain control range, respectively, with phase invariance maintained over PVT. Implemented in GF 8HP BiCMOS technology, the VGAs achieve 18dB nominal gain, 4GHz bandwidth, and IP1dB > -13dBm while consuming 35mW.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"83 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114035881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
A mixer frontend for a four-channel Modulated Wideband Converter with 62 dB blocker rejection 具有62 dB阻滞器抑制的四通道调制宽带转换器的混频器前端
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2016-05-22 DOI: 10.1109/RFIC.2016.7508307
D. Adams, Yonina C. Eldar, B. Murmann
{"title":"A mixer frontend for a four-channel Modulated Wideband Converter with 62 dB blocker rejection","authors":"D. Adams, Yonina C. Eldar, B. Murmann","doi":"10.1109/RFIC.2016.7508307","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508307","url":null,"abstract":"The Modulated Wideband Converter promises to improve receiver flexibility for cognitive radios by leveraging compressive sensing techniques. We present a prototype IC that adds signal reception to previously demonstrated signal detection. Refactoring the mixing sequence between detection and reception enables targeted reception and blocker rejection. We algorithmically design a three-level mixing sequence and additionally employ delay-based harmonic cancellation. When applied together in our 65-nm chip, we measure 62 dB of in-band blocker rejection, while receiving up to four channels between 0 and 900 MHz.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117087599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
0.84-THz imaging pixel with a lock-in amplifier in CMOS 0.84太赫兹成像像素与CMOS中的锁定放大器
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2016-05-22 DOI: 10.1109/RFIC.2016.7508277
R. Xu, Ja-yol Lee, D. Kim, Shinwoong Park, Z. Ahmad, K. O. Kenneth
{"title":"0.84-THz imaging pixel with a lock-in amplifier in CMOS","authors":"R. Xu, Ja-yol Lee, D. Kim, Shinwoong Park, Z. Ahmad, K. O. Kenneth","doi":"10.1109/RFIC.2016.7508277","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508277","url":null,"abstract":"An 840-GHz Schottky diode detector is integrated with an analog lock-in amplifier in 130-nm bulk CMOS. The integrated lock-in amplifier can support a modulation frequency of up to 10 MHz with a gain of 54 dB, a dynamic range of 42 dB, and an input referred noise of less than 10 nV/√(Hz) at modulation frequencies higher than 100 kHz. The integrated lock-in amplifier occupies an area of 0.17 mm2 and consumes 4.9 mA from a 1.2-V supply. The detector and on-chip lock-in amplifier combination was used to form terahertz images.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123280030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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