发布求助
文献互助 智能选刊 最新文献

2019 Forum for Specification and Design Languages (FDL)最新文献

筛选
英文 中文
Systematic RISC-V based Firmware Design⋆ 基于RISC-V的系统固件设计
2019 Forum for Specification and Design Languages (FDL) Pub Date : 2019-09-01 DOI: 10.1109/FDL.2019.8876945
V. Herdt, Daniel Große, R. Drechsler, Christoph Gerum, Alexander Jung, Joscha Benz, O. Bringmann, Michael Schwarz, D. Stoffel, W. Kunz
{"title":"Systematic RISC-V based Firmware Design⋆","authors":"V. Herdt, Daniel Große, R. Drechsler, Christoph Gerum, Alexander Jung, Joscha Benz, O. Bringmann, Michael Schwarz, D. Stoffel, W. Kunz","doi":"10.1109/FDL.2019.8876945","DOIUrl":"https://doi.org/10.1109/FDL.2019.8876945","url":null,"abstract":"Small embedded devices are highly specialized plat forms that integrate several peripherals alongside the CPU core. Embedded devices extensively rely on Firmware (FW) to control and access the peripherals as well as other important functionality. This poses challenges to FW development since the FW must be adapted to each specific device configuration. Besides ensuring functional correctness to avoid errors and security vulnerabilities, an important design factor today is the control and adaptivity of a system with respect to non-functional properties, like for example application-specific timing budgets. Furthermore, optimizations of the FW and HW/SW interface play a very important role due to the tight resource constraints of small embedded devices. To satisfy these requirements new FW design methods are needed targeting FW generation, FW verification and FW optimization.This paper presents such new methods to enable an early, efficient and systematic FW design taking the underlying HW architecture into account. We use the RISC-V Instruction Set Architecture (ISA) as a case study to demonstrate our methods.","PeriodicalId":162747,"journal":{"name":"2019 Forum for Specification and Design Languages (FDL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126995028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Backend Tool for the Integration of Memory Optimizations into Embedded Software 嵌入式软件中内存优化集成的后端工具
2019 Forum for Specification and Design Languages (FDL) Pub Date : 2019-09-01 DOI: 10.1109/FDL.2019.8876895
Manuel Strobel, M. Radetzki
{"title":"A Backend Tool for the Integration of Memory Optimizations into Embedded Software","authors":"Manuel Strobel, M. Radetzki","doi":"10.1109/FDL.2019.8876895","DOIUrl":"https://doi.org/10.1109/FDL.2019.8876895","url":null,"abstract":"Higher functionality combined with increasingly data-hungry and more complex applications make embedded system design steadily more complex. This situation, however, is in direct contrast to development effort in terms of cost and time. A central pillar to face these challenges is system design automation. In this context and regarding increasingly software-centric embedded applications, this work presents a design automation tool for the transparent integration of memory subsystem optimization results into the embedded software at hand. Our solution is based on the LLVM backend and neatly integrated into the LLVM low-level compiler llc. In this paper, the workflow of our code generation method is described in general and further discussed on the example of a concrete implementation for the ARMv6-M architecture. Experiments for this platform and using 10 representative embedded benchmarks prove the functionality of our method by targeted tests and show the successful application of the tool to selected use cases from the field of memory subsystem optimization.","PeriodicalId":162747,"journal":{"name":"2019 Forum for Specification and Design Languages (FDL)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130448803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
RTL Assertion Mining with Automated RTL-to-TLM Abstraction 基于自动RTL到tlm抽象的RTL断言挖掘
2019 Forum for Specification and Design Languages (FDL) Pub Date : 2019-09-01 DOI: 10.1109/FDL.2019.8876941
Tara Ghasempouri, Alessandro Danese, G. Pravadelli, N. Bombieri, J. Raik
{"title":"RTL Assertion Mining with Automated RTL-to-TLM Abstraction","authors":"Tara Ghasempouri, Alessandro Danese, G. Pravadelli, N. Bombieri, J. Raik","doi":"10.1109/FDL.2019.8876941","DOIUrl":"https://doi.org/10.1109/FDL.2019.8876941","url":null,"abstract":"We present a three-step flow to improve Assertion-based Verification methodology with integrated RTL-to-TLM abstraction: First, an automatic assertion miner generates a large set of possible assertions from an RTL design. Second, automatic assertion qualification identifies the most interesting assertions from this set. Third, the assertions are abstracted to the transaction level, such that they can be re-used in TLM verification. We show that the proposed flow automatically chooses the best assertions among the ones generated to verify the design components when abstracted from RTL to TLM. Our experimental results indicate that the proposed methodology allows us to re-use the most interesting set at TLM without relying on any time consuming or error-prone manual transformations with a considerable amount of speed up and considerable reduction in the execution time.","PeriodicalId":162747,"journal":{"name":"2019 Forum for Specification and Design Languages (FDL)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133197567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Functional Coverage-Driven Characterization of RF Amplifiers 射频放大器的功能覆盖驱动特性
2019 Forum for Specification and Design Languages (FDL) Pub Date : 2019-09-01 DOI: 10.1109/FDL.2019.8876957
Muhammad Hassan, Daniel Große, T. Vörtler, K. Einwich, R. Drechsler
{"title":"Functional Coverage-Driven Characterization of RF Amplifiers","authors":"Muhammad Hassan, Daniel Große, T. Vörtler, K. Einwich, R. Drechsler","doi":"10.1109/FDL.2019.8876957","DOIUrl":"https://doi.org/10.1109/FDL.2019.8876957","url":null,"abstract":"In this paper we propose the first functional coverage-driven characterization approach as a systematic solution for the class of Radio Frequency (RF) amplifiers. We elevate the main concepts of digital functional coverage to the context of SystemC AMS in particular, and system-level simulations in general. To enable AMS functional coverage-driven characterization, we introduce two coverage refinement parameters on input and output side, to systematically generate input stimuli and capture specifications. At the heart of the approach is the coverage analysis which measures the functional coverage of the DUV and provides clear feedback to reach coverage closure. We provide a case study using an industrial RF transmitter and receiver model to demonstrate the applicability and efficacy of our approach.","PeriodicalId":162747,"journal":{"name":"2019 Forum for Specification and Design Languages (FDL)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129524303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Exact Synthesis of LTL Properties from Traces 从轨迹精确合成 LTL 属性
2019 Forum for Specification and Design Languages (FDL) Pub Date : 2019-09-01 DOI: 10.1109/FDL.2019.8876900
Heinz Riener
{"title":"Exact Synthesis of LTL Properties from Traces","authors":"Heinz Riener","doi":"10.1109/FDL.2019.8876900","DOIUrl":"https://doi.org/10.1109/FDL.2019.8876900","url":null,"abstract":"We present an exact approach to synthesize temporal-logic formulas in linear temporal logic (LTL) from a set of given positive and negative example traces. Our approach uses topology structures, in particular partial DAGs, to partition the search space into small and manageable subproblems. The algorithm then solves each subproblem independently with the aid of an oracle for deciding satisfiability modulo propositional logic. This strategy is capable of achieving a super-linear speedup when parallelized. We have implemented a bounded synthesis approach to find an LTL formula of minimum size using the proposed topology-guided exact synthesis approach. In an experimental evaluation, we show that the proposed approach achieves a 20× runtime improvement over the state-of-the-art approach.","PeriodicalId":162747,"journal":{"name":"2019 Forum for Specification and Design Languages (FDL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130895956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Deterministic Actors 确定的演员
2019 Forum for Specification and Design Languages (FDL) Pub Date : 2019-09-01 DOI: 10.1109/FDL.2019.8876922
Marten Lohstroh, Edward A. Lee
{"title":"Deterministic Actors","authors":"Marten Lohstroh, Edward A. Lee","doi":"10.1109/FDL.2019.8876922","DOIUrl":"https://doi.org/10.1109/FDL.2019.8876922","url":null,"abstract":"Actors have become widespread in programming languages and programming frameworks focused on parallel and distributed computing. While actors provide a more disciplined model for concurrency than threads, their interactions, if not constrained, admit nondeterminism. As a consequence, actor programs may exhibit unintended behaviors and are less amenable to rigorous testing. We show that nondeterminism can be handled in a number of ways, surveying dataflow dialects, process networks, synchronous-reactive models, and discrete-event models. These existing approaches, however, tend to require centralized control, pose challenges to modular system design, or introduce a single point of failure. We describe “reactors,” a new coordination model that combines ideas from several of the aforementioned approaches to enable determinism while preserving much of the style of actors. Reactors promote modularity and allow for distributed execution. By using a logical model of time that can be associated with physical time, reactors also admit control over timing.","PeriodicalId":162747,"journal":{"name":"2019 Forum for Specification and Design Languages (FDL)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114822716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A methodology to compute long-term fault resilience of NoCs under fault-tolerant routing algorithms 容错路由算法下noc长期故障恢复能力的计算方法
2019 Forum for Specification and Design Languages (FDL) Pub Date : 2019-09-01 DOI: 10.1109/FDL.2019.8876904
Jie Hou, M. Radetzki
{"title":"A methodology to compute long-term fault resilience of NoCs under fault-tolerant routing algorithms","authors":"Jie Hou, M. Radetzki","doi":"10.1109/FDL.2019.8876904","DOIUrl":"https://doi.org/10.1109/FDL.2019.8876904","url":null,"abstract":"Networks-on-Chips (NoCs) are the preferred communication interconnect for many-core systems. Technology scaling increases the susceptibility to failures in the NoC’s components. Fault-tolerant routing algorithms are applied to maintain reliable operation in the presence of such failures. Fault resilience is a measure of a NoC’s ability to tolerate faults. In this paper, we investigate how fault resilience develops over a long period of time during which faults appear and disappear. We apply Markov reward models to investigate long-term fault-resilience of mesh-based NoCs under three different routing algorithms. Fault-tolerant XY routing brings the best long-term fault resilience even though it is less adaptive than fault-tolerant negative-first routing. We further investigate how long-term fault resilience develops with scaling towards larger NoCs.","PeriodicalId":162747,"journal":{"name":"2019 Forum for Specification and Design Languages (FDL)","volume":"418 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122119432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Languages and Formalisms to Enable EDA Techniques in the Context of Industry 4.0 工业4.0背景下实现EDA技术的语言和形式化
2019 Forum for Specification and Design Languages (FDL) Pub Date : 2019-09-01 DOI: 10.1109/FDL.2019.8876899
Stefano Spellini, Roberta Chirico, M. Lora, F. Fummi
{"title":"Languages and Formalisms to Enable EDA Techniques in the Context of Industry 4.0","authors":"Stefano Spellini, Roberta Chirico, M. Lora, F. Fummi","doi":"10.1109/FDL.2019.8876899","DOIUrl":"https://doi.org/10.1109/FDL.2019.8876899","url":null,"abstract":"This paper analyzes a set of languages and standard used when designing industrial plants. It focuses on AutomationML and B2MML to specify respectively the architecture and the intended production of the system being designed. It also relies on the DIN 8580 standard to describe the actions performed by each machine composing the production line.Then, it outlines a methodology starting by mapping the information expressed by the analyzed languages and standards into the Assume-Guarantee Contracts formalism. It exploits contract-based design concepts to tackle the increase automation of the industrial plant design process and to enable the generation of digital twins. The approach is outlined by showing its applicability to a concrete manufacturing scenario.","PeriodicalId":162747,"journal":{"name":"2019 Forum for Specification and Design Languages (FDL)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127725319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
首页 上一页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信