2019 Forum for Specification and Design Languages (FDL)最新文献

Simulation Acceleration of Image Filtering on CMOS Vision Chips Using Many-Core Processors 基于多核处理器的CMOS视觉芯片图像滤波仿真加速

2019 Forum for Specification and Design Languages (FDL) Pub Date : 2019-09-03 DOI: 10.1109/FDL.2019.8876903

G. Doménech-Asensi, T. Kazmierski

引用次数: 0

Syntax-Guided Enumeration of Temporal Properties 时态属性的语法引导枚举

2019 Forum for Specification and Design Languages (FDL) Pub Date : 2019-09-01 DOI: 10.1109/FDL.2019.8876892

Gianluca Martino, G. Fey

引用次数: 2

Security Driven Design Space Exploration for Embedded Systems 嵌入式系统的安全驱动设计空间探索

2019 Forum for Specification and Design Languages (FDL) Pub Date : 2019-09-01 DOI: 10.1109/FDL.2019.8876944

Lukas Gressl, C. Steger, U. Neffe

{"title":"Security Driven Design Space Exploration for Embedded Systems","authors":"Lukas Gressl, C. Steger, U. Neffe","doi":"10.1109/FDL.2019.8876944","DOIUrl":"https://doi.org/10.1109/FDL.2019.8876944","url":null,"abstract":"With the advent of the Internet of Things (IoT) and Cyber Physical Systems (CPS), embedded devices have been gaining importance in our daily lives, as well as industrial processes. Independent of their usage, be it within an IoT system or a CPS, embedded devices are always an attractive target for security attacks, largely due to their continuous network availability and the importance of the data they handle. Thus, the design of such systems requires a thorough consideration of the various security constraints they are liable to. Introducing these security constraints, next to other requirements (e.g. power consumption, performance, etc.), increases the number of design choices that must be taken. As the various constraints are often conflicting each other, designers are faced with the complex task of balancing them. To support a system designer in this job, Design Space Exploration (DSE) tools can be facilitated. However, available DSE tools only offer a limited way of considering security constraints during the design process. In this paper we introduce a novel DSE framework, which allows the consideration of security constraints, in the form of attack scenarios, and attack mitigations, in the form of security tasks. Based on the descriptions of the system’s functionality and architecture, possible attacks, and known mitigation techniques, the framework finds the optimal design for an secure IoT device or CPS. Our framework’s functionality and its benefits are shown based on the design of a secure sensor system.","PeriodicalId":162747,"journal":{"name":"2019 Forum for Specification and Design Languages (FDL)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124669152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Efficient Simulation and Parametrization of Stochastic Petri Nets in SystemC: A Case study from Systems Biology SystemC中随机Petri网的有效模拟和参数化:一个来自系统生物学的案例研究

2019 Forum for Specification and Design Languages (FDL) Pub Date : 2019-09-01 DOI: 10.1109/FDL.2019.8876940

S. Caligola, Tommaso Carlucci, F. Fummi, C. Laudanna, G. Constantin, N. Bombieri, R. Giugno

{"title":"Efficient Simulation and Parametrization of Stochastic Petri Nets in SystemC: A Case study from Systems Biology","authors":"S. Caligola, Tommaso Carlucci, F. Fummi, C. Laudanna, G. Constantin, N. Bombieri, R. Giugno","doi":"10.1109/FDL.2019.8876940","DOIUrl":"https://doi.org/10.1109/FDL.2019.8876940","url":null,"abstract":"Stochastic Petri nets (SPN) are a form of Petri net where the transitions fire after a probabilistic and randomly determined delay. They are adopted in a wide range of applications thanks to their capability of incorporating randomness in the models and taking into account possible fluctuations and environmental noise. In Systems Biology, they are becoming a reference formalism to model metabolic networks, in which the noise due to molecule interactions in the environment plays a crucial role. Some frameworks have been proposed to implement and dynamically simulate SPN. Nevertheless, they do not allow for automatic model parametrization, which is a crucial task to identify the network configurations that lead the model to satisfy temporal properties of the model. This paper presents a framework that synthesizes the SPN models into SystemC code. The framework allows the user to formally define the network properties to be observed and to automatically extrapolate, through Assertion-based Verification (ABV), the parameter configurations that lead the network to satisfy such properties. We applied the framework to implement and simulate a complex biological network, i.e., the purine metabolism, with the aim of reproducing the metabolomics data obtained in-vitro from naive lymphocytes and autoreactive T cells implicated in the induction of experimental autoimmune disorders.","PeriodicalId":162747,"journal":{"name":"2019 Forum for Specification and Design Languages (FDL)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132558249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

WIP on a Coordination Language to Automate the Generation of Co-Simulations 协同仿真自动生成的协调语言的WIP

2019 Forum for Specification and Design Languages (FDL) Pub Date : 2019-09-01 DOI: 10.1109/FDL.2019.8876914

G. Liboni, Julien Deantoni

引用次数: 0

A Multi-Rate Precision Timed Programming Language for Multi-Cores 一种多核多速率精确定时编程语言

2019 Forum for Specification and Design Languages (FDL) Pub Date : 2019-09-01 DOI: 10.1109/FDL.2019.8876950

A. Girault, N. Hili, E. Jenn, Eugene Yip

{"title":"A Multi-Rate Precision Timed Programming Language for Multi-Cores","authors":"A. Girault, N. Hili, E. Jenn, Eugene Yip","doi":"10.1109/FDL.2019.8876950","DOIUrl":"https://doi.org/10.1109/FDL.2019.8876950","url":null,"abstract":"PREcision Timed (PRET) is a conceptual solution proposed in 2007 to address the ever increasing unpredictability of embedded processors, which results from features such as multi-level caches or deep pipelines. For many real-time systems, it is mandatory to compute a strict bound on the program’s execution time. Yet, in general, computing a tight bound is extremely difficult. The rationale of PRET is to simplify both the programming language and the execution platform to allow precise execution times to be easily computed. ForeC is a PRET programming language. It is a multithreaded variant of C with a synchronous execution semantics. ForeC programs are designed to be executed on multi-core processors, built around either PRET cores or classical cores. A drawback of ForeC is that programs are single rate, i.e., all reactions must be implemented to run at the fastest rate imposed by the environment. This represents a high overhead, both at design time and at run-time. In this paper, we propose a multi-rate version of ForeC to improve its practicality and usability for industrial acceptance. We detail the syntax and semantics of the ForeC language in the context of multi-rate applications and present an implementation on a PRET multi-core architecture. Both the languages and its implementation are illustrated over a robotic application.","PeriodicalId":162747,"journal":{"name":"2019 Forum for Specification and Design Languages (FDL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133573121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Towards Object-Oriented Modeling in SCCharts 面向对象的SCCharts建模

2019 Forum for Specification and Design Languages (FDL) Pub Date : 2019-09-01 DOI: 10.1109/FDL.2019.8876901

Alexander Schulz-Rosengarten, Steven Smyth, Michael Mendler

{"title":"Towards Object-Oriented Modeling in SCCharts","authors":"Alexander Schulz-Rosengarten, Steven Smyth, Michael Mendler","doi":"10.1109/FDL.2019.8876901","DOIUrl":"https://doi.org/10.1109/FDL.2019.8876901","url":null,"abstract":"Object orientation is a powerful and widely used paradigm for abstraction and structuring in programming. Many languages are designed with this principle or support different degrees of object orientation. In synchronous languages, originally developed to design embedded reactive systems, there are only few object-oriented influences. However, especially in combination with a statechart notation, the modeling process can be improved by facilitating object orientation as we argue here. At the same time the graphical representation can be used to illustrate the object-oriented design of a system. Synchronous statechart dialects, such as the SCCharts language, provide deterministic concurrency for specifying safety-critical systems. Using SCCharts as an example, we illustrate how an object-oriented modeling approach that supports inheritance, can be introduced. We further present how external, i. e. host language, objects can be included in the SCCharts language. Specifically, we discuss how the recently developed concepts of scheduling directives and scheduling policies can be used to ensure the determinism of objects while retaining encapsulation.","PeriodicalId":162747,"journal":{"name":"2019 Forum for Specification and Design Languages (FDL)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125966809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Chatbot-based assertion generation from natural language specifications 根据自然语言规范生成基于聊天机器人的断言

2019 Forum for Specification and Design Languages (FDL) Pub Date : 2019-09-01 DOI: 10.1109/FDL.2019.8876925

Oliver Keszöcze, I. Harris

引用次数: 5

Formal Design, Co-Simulation and Validation of a Radar Signal Processing System 雷达信号处理系统的形式化设计、联合仿真与验证

2019 Forum for Specification and Design Languages (FDL) Pub Date : 2019-09-01 DOI: 10.1109/FDL.2019.8876905

George Ungureanu, Timmy Sundström, A. Ahlander, I. Sander, I. Söderquist

{"title":"Formal Design, Co-Simulation and Validation of a Radar Signal Processing System","authors":"George Ungureanu, Timmy Sundström, A. Ahlander, I. Sander, I. Söderquist","doi":"10.1109/FDL.2019.8876905","DOIUrl":"https://doi.org/10.1109/FDL.2019.8876905","url":null,"abstract":"With the ever increasing complexity in safety-critical and performance-demanding application domains such as automotive and avionics, the costs of designing, producing and especially testing systems does not scale well for the next generation of applications. One example is the active electronically scanned array (AESA) antenna signal processing chain, which is currently out-of-reach from consumer products but rather part of a few exclusive hi-tech appliances. To cope with the associated complexity of such systems, we propose a design flow starting from a high-level formal modeling language which captures and exposes important design properties to enable their systematic exploitation for the purpose of simulation, analysis and synthesis towards cost-efficient implementations. We demonstrate the capabilities of this approach by providing a compact yet expressive description of the AESA signal processing chain, generate automatic test-cases to verify the conformity of model with design specifications, synthesize a part of it to VHDL and co-simulate the generated artifact to validate its correctness.","PeriodicalId":162747,"journal":{"name":"2019 Forum for Specification and Design Languages (FDL)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114632459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Time Measurement and Control Blocks for Bare-Metal C++ Applications 用于裸金属c++应用程序的时间测量和控制块

2019 Forum for Specification and Design Languages (FDL) Pub Date : 2019-09-01 DOI: 10.1109/FDL.2019.8876898

Friederike Bruns, Irune Yarza, Philipp Ittershagen, Kim Grüttner

引用次数: 2