Syntax-Guided Enumeration of Temporal Properties

We propose Syntax-Guided Property Enumeration, a method for automatically obtaining a set of short and readable temporal logic properties from sequential logic networks. Each property is a temporal logic formula which describes a relation between the primary inputs, the primary outputs, and the latches of the network over time. The approach is applicable to any temporal logic for which decision procedures for model-checking and satisfiability are available. In a case study, we analyze a generic USB controller and compare the results to the well-known previous approach GoldMine. We demonstrate how the flexibility of this approach helps the designer obtain different perspectives of the design under analysis. Useful applications are debugging, reverse engineering, security analysis, or specification mining.