International Journal of Reconfigurable and Embedded Systems (IJRES)最新文献_第8页

Emotion classification for musical data using deep learning techniques 使用深度学习技术对音乐数据进行情感分类

International Journal of Reconfigurable and Embedded Systems (IJRES) Pub Date : 2023-07-01 DOI: 10.11591/ijres.v12.i2.pp240-247

Gaurav Agarwal, Sachi Gupta, Shivani Agarwal, Aul Kumar Rai

{"title":"Emotion classification for musical data using deep learning techniques","authors":"Gaurav Agarwal, Sachi Gupta, Shivani Agarwal, Aul Kumar Rai","doi":"10.11591/ijres.v12.i2.pp240-247","DOIUrl":"https://doi.org/10.11591/ijres.v12.i2.pp240-247","url":null,"abstract":"This research is done based on the identification and thorough analyzing musical data that is extracted by the various method. This extracted information can be utilized in the deep learning algorithm to identify the emotion, based on the hidden features of the dataset. Deep learning-based convolutional neural network (CNN) and long short-term memory-gated recurrent unit (LSTM-GRU) models were developed to predict the information from the musical information. The musical dataset is extracted using the fast Fourier transform (FFT) models. The three deep learning models were developed in this work the first model was based on the information of extracted information such as zero-crossing rate, and spectral roll-off. Another model was developed on the information of Mel frequencybased cepstral coefficient (MFCC) features, the deep and wide CNN algorithm with LSTM-GRU bidirectional model was developed. The third model was developed on the extracted information from Mel-spectrographs and untied these graphs based on two-dimensional (2D) data information to the 2D CNN model alongside LSTM models. Proposed model performance on the information from Mel-spectrographs is compared on the F1 score, precision, and classification report of the models. Which shows better accuracy with improved F1 and recall values as compared with existing approaches.","PeriodicalId":158991,"journal":{"name":"International Journal of Reconfigurable and Embedded Systems (IJRES)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122858428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Turbo encoder and decoder chip design and FPGA device analysis for communication system 通信系统Turbo编解码器芯片设计及FPGA器件分析

International Journal of Reconfigurable and Embedded Systems (IJRES) Pub Date : 2023-07-01 DOI: 10.11591/ijres.v12.i2.pp174-185

Aakanksha Devrari, Adesh Kumar

{"title":"Turbo encoder and decoder chip design and FPGA device analysis for communication system","authors":"Aakanksha Devrari, Adesh Kumar","doi":"10.11591/ijres.v12.i2.pp174-185","DOIUrl":"https://doi.org/10.11591/ijres.v12.i2.pp174-185","url":null,"abstract":"Turbo codes are error-correcting codes with performance that is close to the Shannon theoretical limit (SHA). The motivation for using turbo codes is that the codes are an appealing mix of a random appearance on the channel and a physically realizable decoding structure. The communication systems have the problem of latency, fast switching, and reliable data transfer. The objective of the research paper is to design and turbo encoder and decoder hardware chip and analyze its performance. Two convolutional codes are concatenated concurrently and detached by an interleaver or permuter in the turbo encoder. The expected data from the channel is interpreted iteratively using the two related decoders. The soft (probabilistic) data about an individual bit of the decoded structure is passed in each cycle from one elementary decoder to the next, and this information is updated regularly. The performance of the chip is also verified using the maximum a posteriori (MAP) method in the decoder chip. The performance of field-programmable gate array (FPGA) hardware is evaluated using hardware and timing parameters extracted from Xilinx ISE 14.7. The parallel concatenation offers a better global rate for the same component code performance, and reduced delay, low hardware complexity, and higher frequency support.","PeriodicalId":158991,"journal":{"name":"International Journal of Reconfigurable and Embedded Systems (IJRES)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114073897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Research, challenges and opportunities in software define radio technologies 软件领域的研究、挑战和机遇定义了无线电技术

International Journal of Reconfigurable and Embedded Systems (IJRES) Pub Date : 2023-07-01 DOI: 10.11591/ijres.v12.i2.pp260-268

Jacob Abraham, Kanagaraj Venusamy, A. Judice, Joel Livin A. Obtained, Hameed Shaik, K. Suriyan

引用次数: 0

Development of magnetic levitation system with position and orientation control 具有位置和方向控制的磁悬浮系统的研制

International Journal of Reconfigurable and Embedded Systems (IJRES) Pub Date : 2023-07-01 DOI: 10.11591/ijres.v12.i2.pp287-296

Siti Juliana Abu Bakar, Koay J-Shenn, P. Goh, N. S. Ahmad

引用次数: 0

Video saliency-detection using custom spatiotemporal fusion method 基于自定义时空融合方法的视频显著性检测

International Journal of Reconfigurable and Embedded Systems (IJRES) Pub Date : 2023-07-01 DOI: 10.11591/ijres.v12.i2.pp269-275

Vinay C. Warad, Ruksar Fatima

引用次数: 0

Heart failure prediction based on random forest algorithm using genetic algorithm for feature selectio 基于随机森林的心衰预测算法，采用遗传算法进行特征选择

International Journal of Reconfigurable and Embedded Systems (IJRES) Pub Date : 2023-07-01 DOI: 10.11591/ijres.v12.i2.pp205-214

Yudi Ramdhani, Cakra Mahendra Putra, D. Alamsyah

{"title":"Heart failure prediction based on random forest algorithm using genetic algorithm for feature selectio","authors":"Yudi Ramdhani, Cakra Mahendra Putra, D. Alamsyah","doi":"10.11591/ijres.v12.i2.pp205-214","DOIUrl":"https://doi.org/10.11591/ijres.v12.i2.pp205-214","url":null,"abstract":"A disorder or illness called heart failure results in the heart becoming weak or damaged. In order to avoid heart failure early on, it is crucial to understand the causes of heart failure. Based on validation, two experimental processing steps will be applied to the dataset of clinical records related to heart failure. Testing will be done in the first step utilizing six different classification algorithms, including K-nearest neighbor, neural network, random forest, decision tree, Naïve Bayes, and support vector machine (SVM). Cross-validation was employed to conduct the test. According to the results, the random forest algorithm performed better than the other five algorithms in tests employing the algorithm. Subsequent testing uses an algorithm with the best accuracy value, which will then be tested again using split validation with varying split ratios and genetic algorithms as a selection feature. The value generated from testing using the genetic algorithm selection feature is better than the random forest algorithm alone, which is recorded to produce an accuracy value of 93.36% in predicting the survival of heart failure patients.","PeriodicalId":158991,"journal":{"name":"International Journal of Reconfigurable and Embedded Systems (IJRES)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122083036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

FPGA-based fault analysis for 7-level switched ladder multi-level inverter using decision tree algorithm 基于fpga的7电平梯形多电平逆变器故障分析

International Journal of Reconfigurable and Embedded Systems (IJRES) Pub Date : 2023-07-01 DOI: 10.11591/ijres.v12.i2.pp157-164

Nithya Ramalingam, Anitha Thiagarajan

{"title":"FPGA-based fault analysis for 7-level switched ladder multi-level inverter using decision tree algorithm","authors":"Nithya Ramalingam, Anitha Thiagarajan","doi":"10.11591/ijres.v12.i2.pp157-164","DOIUrl":"https://doi.org/10.11591/ijres.v12.i2.pp157-164","url":null,"abstract":"The proposed method involves the fault analysis of the inverter switches present in the multi-level inverter (MLI) circuitry. The decision tree machine learning algorithm is incorporated for the fault analysis of the inverter switches. The multi-level inverter utilized in this work is a 7-level switched ladder multi-level inverter. There is 4 number of switches in the design of a 7-level inverter driven by the non-carrier digital pulse width modulation signals. The non-carried-based digital pulse-width modulator (DPWM) generation is generated using the event angle for the 7-level of the switched ladder inverter. The proposed method investigates the stuck-at-fault occurrences of the 4 switches in the inverter by manipulating the decision tree parameters such as entropy, information gain, and decision tree. Based on the decision tree, the very high-speed integrated circuit hardware description language (VHDL) code is developed by making use of the behavioral modeling and validated for the power, area in the Xilinx Vivado tool. The real-time feasibility is verified for the proposed method by synthesizing the developed VHDL code in the field programmable gate array (FPGA) device.","PeriodicalId":158991,"journal":{"name":"International Journal of Reconfigurable and Embedded Systems (IJRES)","volume":"82 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121212405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Analysis of frequency dependent Vedic chanting and its influence on neural activity of humans 频率依赖性吠陀念诵及其对人类神经活动的影响分析

International Journal of Reconfigurable and Embedded Systems (IJRES) Pub Date : 2023-07-01 DOI: 10.11591/ijres.v12.i2.pp230-239

Veera Raghava Swamy Nalluri, V. K. Sonti, G. Sundari

{"title":"Analysis of frequency dependent Vedic chanting and its influence on neural activity of humans","authors":"Veera Raghava Swamy Nalluri, V. K. Sonti, G. Sundari","doi":"10.11591/ijres.v12.i2.pp230-239","DOIUrl":"https://doi.org/10.11591/ijres.v12.i2.pp230-239","url":null,"abstract":"In this paper a novel methodology is proposed to identify and to compare the frequency range of different Vedic chantings from Rig Veda, Yajur Veda, Atharva Veda and Sama Veda. Nowadays in spite of busy schedule and hectic work, the human beings are mostly stressed. To get rid from this stressed state, one of the best solutions is listening Vedic chantings. The alpha brainwaves are in the frequency range of 8-12 Hz under giving relaxation to stressed human being. Three selected samples from each Veda have been processed through the simulation compiler Praat and the parameters like spectral response, pitch, intensity, formants and pulses have observed. In the above identified parameters, the frequency in intensity calculation is taken for each sample. This frequency is compared with the brainwaves for which the frequencies are in the ranges of 0 Hz to >27 Hz (alpha, beta, gamma, theta and delta). The extracted signal frequencies from Vedic chantings are compared with frequencies of brainwaves. Among the four Vedas, the frequencies extracted from Sama Veda lies in alpha frequency range. The remaining is fluctuating from alpha.","PeriodicalId":158991,"journal":{"name":"International Journal of Reconfigurable and Embedded Systems (IJRES)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116010488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reconfigurable linear feedback shift register for wireless communication and coding 用于无线通信和编码的可重构线性反馈移位寄存器

International Journal of Reconfigurable and Embedded Systems (IJRES) Pub Date : 2023-07-01 DOI: 10.11591/ijres.v12.i2.pp195-204

Aakanksha Devrari, Adesh Kumar

{"title":"Reconfigurable linear feedback shift register for wireless communication and coding","authors":"Aakanksha Devrari, Adesh Kumar","doi":"10.11591/ijres.v12.i2.pp195-204","DOIUrl":"https://doi.org/10.11591/ijres.v12.i2.pp195-204","url":null,"abstract":"Linear feedback shift register (LFSR) is the basic building block of the communication system used in different coding, error detection and correction codes, such as gold, low-density parity check (LDPC), polar, and turbo codes. There are simple shift register-based n-bit counters with a few XOR gates that behave pseudo-randomly. The LFSR is used in chip hardware for high-speed operations, error control, and the generation of pseudo-random numbers. The hardware chip design and performance estimation of the LFSR is the problem for specific communication system. The motivation of the work is to generate the Gold code sequence by the integration of two LFSR. The article proposes the hardware chip design and simulation of two 5-bit LFSR modules used for the gold sequence generator applicable for the communication systems. The novelty of the work is that the design is scalable and can be extended based on the requirements of the systems which is synthesized and experimentally verified on the Zynq-7000 field programmable gate array (FPGA) board. The concept of this design is programmable and can be extended to n-bit based on the applications. The work is supported, and formulated using very high speed integrated circuit hardware description language (VHDL) programming in Xilinx ISE 14.7 software.","PeriodicalId":158991,"journal":{"name":"International Journal of Reconfigurable and Embedded Systems (IJRES)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129419623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Optimized load balancing mechanism in parallel computing for workflow in cloud computing environment 优化了云计算环境下工作流并行计算中的负载均衡机制

International Journal of Reconfigurable and Embedded Systems (IJRES) Pub Date : 2023-07-01 DOI: 10.11591/ijres.v12.i2.pp276-286

Asma Anjum, A. Parveen

{"title":"Optimized load balancing mechanism in parallel computing for workflow in cloud computing environment","authors":"Asma Anjum, A. Parveen","doi":"10.11591/ijres.v12.i2.pp276-286","DOIUrl":"https://doi.org/10.11591/ijres.v12.i2.pp276-286","url":null,"abstract":"Cloud computing gives on-demand access to computing resources in metered and powerfully adapted way; it empowers the client to get access to fast and flexible resources through virtualization and widely adaptable for various applications. Further, to provide assurance of productive computation, scheduling of task is very much important in cloud infrastructure environment. Moreover, the main aim of task execution phenomena is to reduce the execution time and reserve infrastructure; further, considering huge application, workflow scheduling has drawn fine attention in business as well as scientific area. Hence, in this research work, we design and develop an optimized load balancing in parallel computation aka optimal load balancing in parallel computing (OLBP) mechanism to distribute the load; at first different parameter in workload is computed and then loads are distributed. Further OLBP mechanism considers makespan time and energy as constraint and further task offloading is done considering the server speed. This phenomenon provides the balancing of workflow; further OLBP mechanism is evaluated using cyber shake workflow dataset and outperforms the existing workflow mechanism.","PeriodicalId":158991,"journal":{"name":"International Journal of Reconfigurable and Embedded Systems (IJRES)","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115562123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0