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Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)最新文献

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Estimation of speed, area, and power of parameterizable, soft IP 估计速度，面积，和功率的参数化，软IP
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.378259
J. Sanghavi, Albert R. Wang
{"title":"Estimation of speed, area, and power of parameterizable, soft IP","authors":"J. Sanghavi, Albert R. Wang","doi":"10.1145/378239.378259","DOIUrl":"https://doi.org/10.1145/378239.378259","url":null,"abstract":"We present a new approach to estimate speed, area, and power of a parameterizable, soft IP. By running the ASIC implementation flow only on selected configurations, we predict the performance for any arbitrary configuration. We exploit performance function decomposability to address the combinatorial explosion challenge. The estimator has been used successfully to configure Xtensa processor cores for numerous embedded SOC designs.","PeriodicalId":154316,"journal":{"name":"Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116317193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Fault characterizations and design-for-testability technique for detecting I/sub DDQ/ faults in CMOS/BiCMOS circuits CMOS/BiCMOS电路中I/sub DDQ/故障检测的故障表征和可测试性设计技术
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.378496
K. Raahemifar, M. Ahmadi
{"title":"Fault characterizations and design-for-testability technique for detecting I/sub DDQ/ faults in CMOS/BiCMOS circuits","authors":"K. Raahemifar, M. Ahmadi","doi":"10.1145/378239.378496","DOIUrl":"https://doi.org/10.1145/378239.378496","url":null,"abstract":"This paper provides the results of a simulation-based fault characterization study of CMOS/BiCMOS logic families. We show that most of the shorts cause l/sub DDQ/ faults, while open defects result in delay or stuck-open faults. We propose a design-for-testability technique for detecting short and bridging faults in CMOS/BiCMOS logic circuits. The impact of this circuit modification on the behavior of the circuit in normal mode is investigated.","PeriodicalId":154316,"journal":{"name":"Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126107163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Application of constraint-based heuristics in collaborative design 约束启发式在协同设计中的应用
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.378533
J. Carballo, S. W. Director
{"title":"Application of constraint-based heuristics in collaborative design","authors":"J. Carballo, S. W. Director","doi":"10.1145/378239.378533","DOIUrl":"https://doi.org/10.1145/378239.378533","url":null,"abstract":"Significant acceleration of today's complex collaborative design processes can be achieved if team members are able to apply search heuristics that consider the simultaneous effect of all design constraints. We present the Active approach to Design Process Management (ADPM), whereby designers receive constraint-based feedback that enables them to apply these search heuristics effectively. To evaluate ADPM, we developed a design process evaluation environment called TeamSim. Evaluation results suggest that ADPM can reduce costly design iterations at the expense of extra, less costly, verification tool executions.","PeriodicalId":154316,"journal":{"name":"Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128500869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Efficient large-scale power grid analysis based on preconditioned Krylov-subspace iterative methods 基于预条件krylov -子空间迭代法的高效大规模电网分析
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.379023
Tsung-Hao Chen, C. C. Chen
{"title":"Efficient large-scale power grid analysis based on preconditioned Krylov-subspace iterative methods","authors":"Tsung-Hao Chen, C. C. Chen","doi":"10.1145/378239.379023","DOIUrl":"https://doi.org/10.1145/378239.379023","url":null,"abstract":"In this paper, we propose preconditioned Krylov-subspace iterative methods to perform efficient DC and transient simulations for large-scale linear circuits with an emphasis on power delivery circuits. We also prove that a circuit with inductors can be simplified from MNA to NA format, and the matrix becomes an s.p.d. matrix. This property makes it suitable for the conjugate gradient with incomplete Cholesky decomposition as the preconditioner, which is faster than other direct and iterative methods. Extensive experimental results on large-scale industrial power grid circuits show that our method is over 200 times faster for DC analysis and around 10 times faster for transient simulation compared to SPICE3. Furthermore, our algorithm reduces over 75% of memory usage than SPICE3 while the accuracy is not compromised.","PeriodicalId":154316,"journal":{"name":"Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127450669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 217
Parallelizing DSP nested loops on reconfigurable architectures using data context switching 利用数据上下文切换在可重构架构上并行化DSP嵌套循环
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.378483
K. Bondalapati
{"title":"Parallelizing DSP nested loops on reconfigurable architectures using data context switching","authors":"K. Bondalapati","doi":"10.1145/378239.378483","DOIUrl":"https://doi.org/10.1145/378239.378483","url":null,"abstract":"Reconfigurable architectures promise significant performance and flexibility advantages over conventional architectures. Automatic mapping techniques that exploit the features of the hardware are needed to leverage the power of these architectures. In this paper, we develop techniques for parallelizing nested loop computations from digital signal processing (DSP) applications onto high performance pipelined configurations. We propose a novel data context switching technique that exploits the embedded distributed memory available in reconfigurable architectures to parallelize such loops. Our technique is demonstrated on two diverse state-of-the-art reconfigurable architectures, namely, Virtex and the Chameleon Systems reconfigurable communications processor. Our techniques show significant performance improvements on both architectures and also perform better than state-of-the-art DSP and microprocessor architectures.","PeriodicalId":154316,"journal":{"name":"Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130572297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
MetaCores: design and optimization techniques metacore:设计和优化技术
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.379028
S. Meguerdichian, F. Koushanfar, A. Mogre, D. Petranovic, M. Potkonjak
{"title":"MetaCores: design and optimization techniques","authors":"S. Meguerdichian, F. Koushanfar, A. Mogre, D. Petranovic, M. Potkonjak","doi":"10.1145/378239.379028","DOIUrl":"https://doi.org/10.1145/378239.379028","url":null,"abstract":"Hardware intellectual property (IP) is delivered at three levels of abstraction: hard, firm, and soft. In order to further enhance performance, efficiency, and flexibility of IP design, we have developed a new approach for designing hardware and software IP called MetaCores. The new design approach starts at the algorithm level and leverages on the algorithm's intrinsic optimization degrees of freedom. The approach has four main components: (i) problem formulation and identification of optimization degrees of freedom, (ii) objective functions and constraints, (iii) cost evaluation engine, and (iv) multiresolution design space search. From the algorithmic viewpoint, the main contribution is the introduction of multiresolution search in algorithm optimization and synthesis process. We have applied the approach to the development of Viterbi and IIR MetaCores. Experimental results demonstrate the effectiveness of the new approach.","PeriodicalId":154316,"journal":{"name":"Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131731994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Symbolic RTL simulation 符号RTL仿真
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1109/DAC.2001.156106
Alfred Kölbl, J. Kukula, R. Damiano
{"title":"Symbolic RTL simulation","authors":"Alfred Kölbl, J. Kukula, R. Damiano","doi":"10.1109/DAC.2001.156106","DOIUrl":"https://doi.org/10.1109/DAC.2001.156106","url":null,"abstract":"Symbolic simulation is a promising formal verification technique combining the flexibility of conventional simulation with powerful symbolic methods. Unfortunately, existing symbolic simulators are restricted to gate level simulation or handle just a synthesizable subset of an HDL. Simulation of systems composed of design, testbench and correctness checkers, however, requires the complete set of HDL constructs. We present an approach that enables symbolic simulation of the complete set of RT-level Verilog constructs with full delay support. Additionally, we propose a flexible scheme for introducing symbolic variables and demonstrate how error traces can be simulated with this new scheme. Finally, we present some experimental results on an 8051 micro-controller design which prove the effectiveness of our approach.","PeriodicalId":154316,"journal":{"name":"Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131861464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
A new gate delay model for simultaneous switching and its applications 一种新的同时开关门延迟模型及其应用
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.378488
Liang-Chi Chen, S. Gupta, M. Breuer
{"title":"A new gate delay model for simultaneous switching and its applications","authors":"Liang-Chi Chen, S. Gupta, M. Breuer","doi":"10.1145/378239.378488","DOIUrl":"https://doi.org/10.1145/378239.378488","url":null,"abstract":"We present a new model to capture the delay phenomena associated with simultaneous to-controlling transitions. The proposed delay model accurately captures the effect of the targeted delay phenomena over a wide range of transition times and skews. It also captures the effects of more variables than table lookup methods can handle. The model helps improve the accuracy of static timing analysis, incremental timing refinement, and timing-based ATPG.","PeriodicalId":154316,"journal":{"name":"Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132805836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 67
Utilizing memory bandwidth in DSP embedded processors 利用DSP嵌入式处理器的内存带宽
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.378520
C. Gebotys
{"title":"Utilizing memory bandwidth in DSP embedded processors","authors":"C. Gebotys","doi":"10.1145/378239.378520","DOIUrl":"https://doi.org/10.1145/378239.378520","url":null,"abstract":"This paper presents a network flow approach to solving the register binding and allocation problem for multi word memory access DSP processors. In recently announced DSP processors, such as Star*core, sixteen bit instructions which simultaneously access four words from memory are supported. A polynomial-time network flow methodology is used to allocate multiword accesses while minimizing code size. Results show that improvements of up to 87% in terms of memory bandwidth (and up to 30% reduction in energy dissipation) are obtained compared to compiler-generated DSP code. This research is important for industry since this value-added technique can increase memory bandwidths and minimize code size without increasing cost.","PeriodicalId":154316,"journal":{"name":"Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122209925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Fast bit-true simulation 快速位真仿真
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.379052
Holger Keding, Martin Coors, O. Lüthje, H. Meyr
{"title":"Fast bit-true simulation","authors":"Holger Keding, Martin Coors, O. Lüthje, H. Meyr","doi":"10.1145/378239.379052","DOIUrl":"https://doi.org/10.1145/378239.379052","url":null,"abstract":"This paper presents a design environment which enables fast simulation of fixed-point signal processing algorithms. In contrast to existing approaches which use C/C++ libraries for the emulation of generic fixed-point data types, this novel approach additionally permits a code transformation to integral data types for fast simulation of the bit-true behavior. A speedup by a factor of 20 to 400 can he achieved compared to library based simulation.","PeriodicalId":154316,"journal":{"name":"Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114965514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
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