Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)最新文献

A novel method for stochastic nonlinearity analysis of a CMOS pipeline ADC 一种新的CMOS流水线ADC随机非线性分析方法

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.378370

D. Goren, Eliyahu Shamsaev, I. Wagner

引用次数: 11

A unified DFT architecture for use with IEEE 1149.1 and VSIA/IEEE P1500 compliant test access controllers 用于IEEE 1149.1和VSIA/IEEE P1500兼容的测试访问控制器的统一DFT体系结构

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.378280

B. Dervisoglu

引用次数: 15

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect 包含寄生双极效应解决方案的SOI domino逻辑的技术映射

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.378527

S. Karandikar, S. Sapatnekar

引用次数: 4

Robust interfaces for mixed-timing systems with application to latency-insensitive protocols 应用延迟不敏感协议的混合时序系统的鲁棒接口

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.378256

Tiberiu Chelcea, S. Nowick

引用次数: 126

LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs LOTTERYBUS:一种用于片上系统设计的新型高性能通信架构

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.378252

K. Lahiri, A. Raghunathan, G. Lakshminarayana

{"title":"LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs","authors":"K. Lahiri, A. Raghunathan, G. Lakshminarayana","doi":"10.1145/378239.378252","DOIUrl":"https://doi.org/10.1145/378239.378252","url":null,"abstract":"The LOTTERYBUS architecture was designed to address the following limitations of current communication architectures: (i) lack of control over the allocation of communication bandwidth to different system components or data flows (e.g., in static priority based shared buses), leading to starvation of lower priority components in some situations, and (ii) significant latencies resulting from variations in the time-profile of the communication requests (e.g., in time division multiplexed access (TDMA) based architectures), sometimes leading to larger latencies for high-priority communications. We present two variations of LOTTERYBUS: the first is a low overhead architecture with statically configured parameters, while the second variant is a more sophisticated architecture, in which values of the architectural parameters are allowed to vary dynamically. Our experiments investigate the performance of the LOTTERYBUS architecture across a wide range of communication traffic characteristics. In addition, we also analyze its performance in a 4/spl times/4 ATM switch sub-system design. The results demonstrate that the LOTTERYBUS architecture is (i) capable of providing the designer with fine grained control over the bandwidth allocated to each SoC component or data flow, and (ii) well suited to provide high priority communication traffic with low latencies (we observed upto 85.4% reduction in communication latencies over conventional on-chip communication architectures).","PeriodicalId":154316,"journal":{"name":"Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)","volume":"14 6 Pt 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123715822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 146

(When) will FPGAs kill ASICs? fpga何时会取代asic ?

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1109/DAC.2001.156159

Rob A. Rutenbar

引用次数: 11

Formal property verification by abstraction refinement with formal, simulation and hybrid engines 通过形式化、仿真和混合引擎进行抽象细化的形式化属性验证

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.378260

Dong Wang, Pei-Hsin Ho, Jiang Long, J. Kukula, Yunshan Zhu, Hi-Keung Tony Ma, R. Damiano

{"title":"Formal property verification by abstraction refinement with formal, simulation and hybrid engines","authors":"Dong Wang, Pei-Hsin Ho, Jiang Long, J. Kukula, Yunshan Zhu, Hi-Keung Tony Ma, R. Damiano","doi":"10.1145/378239.378260","DOIUrl":"https://doi.org/10.1145/378239.378260","url":null,"abstract":"We present RFN, a formal property verification tool based on abstraction refinement. Abstraction refinement is a strategy for property verification. It iteratively refines an abstract model to better approximate the behavior of the original design in the hope that the abstract model alone will provide enough evidence to prove or disprove the property. However, previous work on abstraction refinement was only demonstrated on designs with up to 500 registers. We developed RFN to verify real-world designs that may contain thousands of registers. RFN differs from the previous work in several ways. First, instead of relying on a single engine, RFN employs multiple formal verification engines, including a BDD-ATPG hybrid engine and a conventional BDD-based fixpoint engine, for finding error traces or proving properties on the abstract model. Second, RFN uses a novel two-phase process involving 3-valued simulation and sequential ATPG to determine how to refine the abstract model. Third, RFN avoids the weakness of other abstraction-refinement algorithms-finding error traces on the original design, by utilizing the error trace of the abstract model to guide sequential ATPG to find an error trace on the original design. We implemented and applied a prototype of RFN to verify various properties of real-world RTL designs containing approximately 5,000 registers, which represents an order of magnitude improvement over previous results. On these designs, we successfully proved a few properties and discovered a design violation.","PeriodicalId":154316,"journal":{"name":"Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)","volume":"421 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116402450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 83

False coupling interactions in static timing analysis 静态时序分析中的伪耦合相互作用

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.379055

Ravishankar Arunachalam, R. D. Blanton, L. Pileggi

引用次数: 34

Performance-driven multi-level clustering with application to hierarchical FPGA mapping 性能驱动的多级聚类及其在FPGA分层映射中的应用

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.378532

J. Cong, Michail Romesis

引用次数: 33

A transaction-based unified simulation/emulation architecture for functional verification 用于功能验证的基于事务的统一仿真/仿真体系结构

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Pub Date : 2001-06-22 DOI: 10.1145/378239.379036

M. Kudlugi, S. Hassoun, C. Selvidge, Duaine Pryor

引用次数: 36