发布求助
文献互助 智能选刊 最新文献

2010 International Conference on Microelectronic Test Structures (ICMTS)最新文献

筛选
英文 中文
A test vehicle and a two step procedure to evaluate a massive number of single-walled carbon nanotube field effect transistors 一种评估大量单壁碳纳米管场效应晶体管的测试工具和两步程序
2010 International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2010-03-22 DOI: 10.1109/ICMTS.2010.5466860
I. Martin-Fernandez, M. Sansa, F. Pérez-Murano, P. Godignon, E. Lora-Tamayo
{"title":"A test vehicle and a two step procedure to evaluate a massive number of single-walled carbon nanotube field effect transistors","authors":"I. Martin-Fernandez, M. Sansa, F. Pérez-Murano, P. Godignon, E. Lora-Tamayo","doi":"10.1109/ICMTS.2010.5466860","DOIUrl":"https://doi.org/10.1109/ICMTS.2010.5466860","url":null,"abstract":"We present an automatic testing procedure to evaluate massive amounts of CNT-FETs that have been fabricated as a test vehicle. The procedure has been used to evaluate almost 140,000 CNT-FET devices that had been batch fabricated in a 4 inch wafer. The possibility of using data obtained from the automatic testing to achieve statistical analyses on device fabrication and on device electric characteristic is also analyzed.","PeriodicalId":153086,"journal":{"name":"2010 International Conference on Microelectronic Test Structures (ICMTS)","volume":"158 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133686545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On-chip in-situ measurements of Vth and AC gain of differential pair transistors 差动对晶体管电压增益和交流增益的片上原位测量
2010 International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2010-03-22 DOI: 10.1109/ICMTS.2010.5466809
Y. Bando, S. Takaya, T. Ohkawa, Toshiharu Takaramoto, Toshio Yamada, M. Souda, S. Kumashiro, M. Nagata
{"title":"On-chip in-situ measurements of Vth and AC gain of differential pair transistors","authors":"Y. Bando, S. Takaya, T. Ohkawa, Toshiharu Takaramoto, Toshio Yamada, M. Souda, S. Kumashiro, M. Nagata","doi":"10.1109/ICMTS.2010.5466809","DOIUrl":"https://doi.org/10.1109/ICMTS.2010.5466809","url":null,"abstract":"In-situ DC measurements of individual transistors in a differential pair of an analog amplifier derive threshold voltage, Vth, of 1.0-V transistors in a 90-nm CMOS technology. On-chip continuous time waveform monitoring is used to evaluate AC response of the same amplifier. The distribution of AC gain versus Vth of transistors within amplifiers is captured. The degradation of common-mode rejection property is observed for an amplifier with intentionally introduced mismatches to the pair of transistors.","PeriodicalId":153086,"journal":{"name":"2010 International Conference on Microelectronic Test Structures (ICMTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130553861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An efficient method of calibrating MOSFET capacitances by way of excluding intra- DUT parasitic contributions 通过排除DUT内寄生贡献来校准MOSFET电容的有效方法
2010 International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2010-03-22 DOI: 10.1109/ICMTS.2010.5466828
Y. Naruta, R. Koh, T. Iizuka
{"title":"An efficient method of calibrating MOSFET capacitances by way of excluding intra- DUT parasitic contributions","authors":"Y. Naruta, R. Koh, T. Iizuka","doi":"10.1109/ICMTS.2010.5466828","DOIUrl":"https://doi.org/10.1109/ICMTS.2010.5466828","url":null,"abstract":"An efficient exclusion of intra-DUT parasitic capacitances has been enabled by a combination of capacitance measurement and 3D capacitance simulation on structures with varying number of contacts per side for a MOSFET structure. Accounted for is the capacitance shift due to the presence of contact plugs, the physical shapes of which are not necessarily the same as their geometrical representations in design space.","PeriodicalId":153086,"journal":{"name":"2010 International Conference on Microelectronic Test Structures (ICMTS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121985958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
New RF intrinsic parameters extraction procedure for advanced MOS transistors 新型MOS晶体管射频本征参数提取方法
2010 International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2010-03-22 DOI: 10.1109/ICMTS.2010.5466853
J. Tinoco, A. G. Martinez-Lopez, M. Emam, J. Raskin
{"title":"New RF intrinsic parameters extraction procedure for advanced MOS transistors","authors":"J. Tinoco, A. G. Martinez-Lopez, M. Emam, J. Raskin","doi":"10.1109/ICMTS.2010.5466853","DOIUrl":"https://doi.org/10.1109/ICMTS.2010.5466853","url":null,"abstract":"A new extraction method of the intrinsic parameters of the small-signal equivalent circuit model of SOI MOS transistors (MOSFET) is presented. This new method does not need the previous knowledge of the extrinsic series resistances, moreover, it is possible to directly determine the intrinsic parameters at the bias point of interest. Floating-Body SOI MOSFETs are analyzed using this method.","PeriodicalId":153086,"journal":{"name":"2010 International Conference on Microelectronic Test Structures (ICMTS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124307321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Characterization & modeling of gate-induced-drain-leakage with complete overlap and fringing model 具有完全重叠和边缘模型的栅极诱发漏极特性与建模
2010 International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2010-03-22 DOI: 10.1109/ICMTS.2010.5466816
D. Rideau, V. Quenette, D. Garetto, E. Dornel, M. Weybright, J. Manceau, O. Saxod, C. Tavernier, H. Jaouen
{"title":"Characterization & modeling of gate-induced-drain-leakage with complete overlap and fringing model","authors":"D. Rideau, V. Quenette, D. Garetto, E. Dornel, M. Weybright, J. Manceau, O. Saxod, C. Tavernier, H. Jaouen","doi":"10.1109/ICMTS.2010.5466816","DOIUrl":"https://doi.org/10.1109/ICMTS.2010.5466816","url":null,"abstract":"This paper investigates and models Gate Induced Drain Leakage (GIDL) for a wide variety of high voltage devices with different low doped drain (LDD) structures. Based on TCAD simulations, we propose semi-analytical a pseudo-2D model for Gate induced Drain leakage. This model includes a complete modeling of the overlap region accounting for technological process and bulk bias dependency through detailed electric field description.","PeriodicalId":153086,"journal":{"name":"2010 International Conference on Microelectronic Test Structures (ICMTS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133050635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A universal structure for SRAM cell characterization SRAM单元表征的通用结构
2010 International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2010-03-22 DOI: 10.1109/ICMTS.2010.5466815
Xiaowei Deng, T. Houston, A. Duong, W. Loh
{"title":"A universal structure for SRAM cell characterization","authors":"Xiaowei Deng, T. Houston, A. Duong, W. Loh","doi":"10.1109/ICMTS.2010.5466815","DOIUrl":"https://doi.org/10.1109/ICMTS.2010.5466815","url":null,"abstract":"A universal test structure (UTS) for SRAM cell characterization is proposed and implemented in 65nm -28nm technologies. The structure allows, for the first time, measurement of nearly all transistor and cell characteristics of an SRAM cell on silicon. It hence enables direct correlation among various measured transistor and cell characteristics, collection of intra-bit transistor mismatch data, and assessment of wafer level Vmin sensitivity on transistor characteristics. Measured data are presented.","PeriodicalId":153086,"journal":{"name":"2010 International Conference on Microelectronic Test Structures (ICMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125475315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SIS wide-band model extraction methodology for SOI on-chip inductor SOI片上电感的SIS宽带模型提取方法
2010 International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2010-03-22 DOI: 10.1109/ICMTS.2010.5466850
R. Topaloglu, J. Goo, A. Loke, Michael M. Oshima, S. W. Sim
{"title":"SIS wide-band model extraction methodology for SOI on-chip inductor","authors":"R. Topaloglu, J. Goo, A. Loke, Michael M. Oshima, S. W. Sim","doi":"10.1109/ICMTS.2010.5466850","DOIUrl":"https://doi.org/10.1109/ICMTS.2010.5466850","url":null,"abstract":"On-chip inductors are recently in high demand even for digital applications due to strict jitter and phase noise requirements in oscillators. Accurate and fast modeling techniques are needed to enable low-cost and fast silicon turnaround. We present a fast and accurate methodology named scaled, iterative, and sampled (SIS) non-linear least squares optimization to extract wide-band model parameters suitable up to 20 GHz for inductor. To test our methodology, we implement a silicon-on-insulator (SOI) inductor in a 45 nm technology. The inductor is suitable for 8 to 20 GHz operation with 1.45 nH inductance and a quality factor of 17 at 10 GHz. We correlate our results to silicon measurements and achieve a very good fit between our models and silicon data. With our methodology, we achieve model-turnaround time of a few hours.","PeriodicalId":153086,"journal":{"name":"2010 International Conference on Microelectronic Test Structures (ICMTS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116185148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Influence of metal coverage on transistor mismatch and variability in copper damascene based CMOS technologies 金属覆盖对铜damascene CMOS技术中晶体管失配和可变性的影响
2010 International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2010-03-22 DOI: 10.1109/ICMTS.2010.5466825
N. Wils, H. Tuinhout, M. Meijer
{"title":"Influence of metal coverage on transistor mismatch and variability in copper damascene based CMOS technologies","authors":"N. Wils, H. Tuinhout, M. Meijer","doi":"10.1109/ICMTS.2010.5466825","DOIUrl":"https://doi.org/10.1109/ICMTS.2010.5466825","url":null,"abstract":"This paper summarizes a comprehensive study on the effect of asymmetrical metal coverage on matching performance for a 45 nm copper damascene based CMOS process. We demonstrate that random mismatch fluctuations are not affected by metal layout asymmetries and we provide valuable new insights about the magnitude of systematic mismatches that can be expected due to asymmetrical layouts and CMP tiling. For the first time we also present results on the impact of temperature increases on both systematic as well as random drain current mismatches.","PeriodicalId":153086,"journal":{"name":"2010 International Conference on Microelectronic Test Structures (ICMTS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134415631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Novel test structures for temperature budget determination during wafer processing 用于晶圆加工过程中温度预算测定的新型测试结构
2010 International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2010-03-22 DOI: 10.1109/ICMTS.2010.5466867
E. Faber, R. Wolters, J. Schmitz
{"title":"Novel test structures for temperature budget determination during wafer processing","authors":"E. Faber, R. Wolters, J. Schmitz","doi":"10.1109/ICMTS.2010.5466867","DOIUrl":"https://doi.org/10.1109/ICMTS.2010.5466867","url":null,"abstract":"Temperature is a crucial parameter in many planar technology processing steps. However, the determination of the actual temperature history at the device side of the substrate is not straightforward. We present a novel method for determining the temperature history of the process side of silicon wafers and chips, which is based on well-known silicide formation reactions of metal-Si systems and is determined via (4 point probe) resistance measurements. In this case we explored the Pd-Si system which has a suitable operating range from 100 – 200 °C. We propose a method based on metal layers patterned in different line configurations (using the width and number of the lines as parameters) and anticipate that silicide developments at these structures is geometrically dependent and hence can provide a way for obtaining a refined temperature information. First experiments on bulk Si wafers show that the proposed method yields predictable and stable results.","PeriodicalId":153086,"journal":{"name":"2010 International Conference on Microelectronic Test Structures (ICMTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122455788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A bulk micromachined vertical nano-gap Pirani wide-range pressure test structure for packaged MEMS performance monitoring 一种用于封装MEMS性能监测的大块微机械垂直纳米间隙皮拉尼宽量程压力测试结构
2010 International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2010-03-22 DOI: 10.1109/ICMTS.2010.5466871
M. Kubota, Toshihiro Okada, Y. Mita, M. Sugiyama, Y. Nakano
{"title":"A bulk micromachined vertical nano-gap Pirani wide-range pressure test structure for packaged MEMS performance monitoring","authors":"M. Kubota, Toshihiro Okada, Y. Mita, M. Sugiyama, Y. Nakano","doi":"10.1109/ICMTS.2010.5466871","DOIUrl":"https://doi.org/10.1109/ICMTS.2010.5466871","url":null,"abstract":"A nano-gap Pirani gauge for integration with bulk MEMS sensors and actuators was fabricated by cutting-edge high aspect ratio bulk micromachining. The 150nm-wide, 5000nm-dep vertical trench enables wide-range pressure measurement; the device showed sensitity in all the tested range from 6.3 to 101.3kPa. ±0.27% of power variation around 35 mW was measured for ±1 kPa of pressure change from atmospheric pressure.","PeriodicalId":153086,"journal":{"name":"2010 International Conference on Microelectronic Test Structures (ICMTS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124550878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信