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2010 International Conference on Microelectronic Test Structures (ICMTS)最新文献

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Electrical characterization of novel PMNT thin-films 新型PMNT薄膜的电学特性
2010 International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2010-03-22 DOI: 10.1109/ICMTS.2010.5466848
Wenbin Chen, K. McCarthy, M. Çopuroğlu, S. O’Brien, R. Winfield, A. Mathewson
{"title":"Electrical characterization of novel PMNT thin-films","authors":"Wenbin Chen, K. McCarthy, M. Çopuroğlu, S. O’Brien, R. Winfield, A. Mathewson","doi":"10.1109/ICMTS.2010.5466848","DOIUrl":"https://doi.org/10.1109/ICMTS.2010.5466848","url":null,"abstract":"This paper presents the systematic investigation by electrical characterization of PMNT (lead magnesium niobate - lead titanate, Pb(Mg<sub>0.33</sub>Nb<sub>0.67</sub>)<sub>0.65</sub>Ti<sub>0.35</sub>O<sub>3</sub>) thin-films with different fabrication parameters. The PMNT thin-films are processed under different conditions including annealing at various temperatures. Capacitance-voltage (C-V), current-voltage (I-V), capacitance-frequency (C-F), dissipation factor-frequency (D-F) and complex impedance-frequency (Z-F) measurements are presented.","PeriodicalId":153086,"journal":{"name":"2010 International Conference on Microelectronic Test Structures (ICMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130103909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Test structures for characterization of thermal-mechanical stress in 3D stacked IC for analog design 用于模拟设计的3D堆叠IC中热机械应力表征的测试结构
2010 International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2010-03-22 DOI: 10.1109/ICMTS.2010.5466836
N. Minas, G. van der Plas, H. Oprins, Yu Yang, C. Okoro, A. Mercha, V. Cherman, C. Torregiani, D. Perry, Miro Cupac, M. Rakowski, P. Marchal
{"title":"Test structures for characterization of thermal-mechanical stress in 3D stacked IC for analog design","authors":"N. Minas, G. van der Plas, H. Oprins, Yu Yang, C. Okoro, A. Mercha, V. Cherman, C. Torregiani, D. Perry, Miro Cupac, M. Rakowski, P. Marchal","doi":"10.1109/ICMTS.2010.5466836","DOIUrl":"https://doi.org/10.1109/ICMTS.2010.5466836","url":null,"abstract":"In this paper we present test structures and measurement techniques that enable extraction of significance of effects expected in 3D TSV technologies. The DAC test structure is optimized to detect Ion changes down to 0.5 % due to TSV proximity, TSV orientation, thermal hotspots and wafer thinning/stacking process. The results obtained from the stand-alone MOS devices and the DAC structure clearly indicate the impact of TSV proximity and TSV orientation on the carrier mobility of nearby transistors.","PeriodicalId":153086,"journal":{"name":"2010 International Conference on Microelectronic Test Structures (ICMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131143873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Kelvin resistor structures for the investigation of corner serif Proximity Correction 角衬线邻近校正研究的开尔文电阻结构
2010 International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2010-03-22 DOI: 10.1109/ICMTS.2010.5466866
S. Smith, A. Tsiamis, M. Mccallum, A. Hourd, J. Stevenson, A. Walton
{"title":"Kelvin resistor structures for the investigation of corner serif Proximity Correction","authors":"S. Smith, A. Tsiamis, M. Mccallum, A. Hourd, J. Stevenson, A. Walton","doi":"10.1109/ICMTS.2010.5466866","DOIUrl":"https://doi.org/10.1109/ICMTS.2010.5466866","url":null,"abstract":"Electrical test structures for the characterisation of Optical Proximity Correction (OPC) have been fabricated in thin aluminium using i-line lithography and reactive ion etching. Initial electrical measurements are presented which show an increase in the resistance of a right angled section of Al track as the level of OPC on the inside corner is increased. Structures with OPC applied to the outer corner do not show the same change in resistance. SEM images of similar Al test structures clearly show the effects of applying OPC and suggest that inner corner serif OPC leads to a narrowing of the conducting track.","PeriodicalId":153086,"journal":{"name":"2010 International Conference on Microelectronic Test Structures (ICMTS)","volume":" 1157","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113946669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A unique and accurate extraction technique of the asymmetric bottom-pillar resistance for the vertical MOSFET 一种独特而精确的垂直MOSFET底柱不对称电阻提取技术
2010 International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2010-03-22 DOI: 10.1109/ICMTS.2010.5466812
K. Sakui, T. Endoh
{"title":"A unique and accurate extraction technique of the asymmetric bottom-pillar resistance for the vertical MOSFET","authors":"K. Sakui, T. Endoh","doi":"10.1109/ICMTS.2010.5466812","DOIUrl":"https://doi.org/10.1109/ICMTS.2010.5466812","url":null,"abstract":"The concept of the measurement technique is to separate the paths by at least two directions; one is the current path, where the drain current flows, and the other is the non-current path, where the voltage is measured with the connection to the high-Z gate of the monitor circuit. The proposed measurement technique has been validated by HSPICE simulation.","PeriodicalId":153086,"journal":{"name":"2010 International Conference on Microelectronic Test Structures (ICMTS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114824065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Compact models of parasitic resistance of resistors for analog circuits 模拟电路中电阻器寄生电阻的紧凑模型
2010 International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2010-03-22 DOI: 10.1109/ICMTS.2010.5466818
Kenta Yamada
{"title":"Compact models of parasitic resistance of resistors for analog circuits","authors":"Kenta Yamada","doi":"10.1109/ICMTS.2010.5466818","DOIUrl":"https://doi.org/10.1109/ICMTS.2010.5466818","url":null,"abstract":"Accurate and useful compact models of parasitic resistance of resistors for analog circuits are proposed. The model is applicable to any layout patterns and topologies normally used in analog circuits. In addition, test structures to measure the parasitic resistance correctly are shown and the models are validated for a 40nm CMOS technology.","PeriodicalId":153086,"journal":{"name":"2010 International Conference on Microelectronic Test Structures (ICMTS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129360811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comprehensive quality assurance methodology for BSIM4.5 corner parameter extraction BSIM4.5角参数提取的综合质量保证方法
2010 International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2010-03-22 DOI: 10.1109/ICMTS.2010.5466819
Hiroo Masuda, S. Itoh, H. Koike, N. Wakita, R. Inagaki
{"title":"Comprehensive quality assurance methodology for BSIM4.5 corner parameter extraction","authors":"Hiroo Masuda, S. Itoh, H. Koike, N. Wakita, R. Inagaki","doi":"10.1109/ICMTS.2010.5466819","DOIUrl":"https://doi.org/10.1109/ICMTS.2010.5466819","url":null,"abstract":"Quality assurance of shipped compact model parameters is one of the crucial problems for circuit designers as well as parameter providers in process foundries. However, very few reports have been published on this issue and it is virtually veiled so far. In this paper, we firstly propose a comprehensive methodology focused on corner parameter assessment for compact MOS models. Key technologies are: (1) rational target description of corner performances, (2) a new quantitative error definition of target performances, and (3) quality assurance strategy which can leads to a standardization scheme in parameter extraction framework. The new QA technology was verified with 90nm BSIM4.5 corner MOS model parameters. This activity has been supported by five companies who applied to STARC corner-parameter extraction contest using identical I-V and C-V experimental data and corner-performance specifications. The result shows significant features that the quality of the corner-parameters is widely spread in terms of accuracy. Our new definition of allover RMS error is found to range 1.32% to 11.18% depending on the corner-parameters from contest applicants. Note that this work will give a new quantitative flow & algorithm for comprehensive corner parameter assessment.","PeriodicalId":153086,"journal":{"name":"2010 International Conference on Microelectronic Test Structures (ICMTS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116238373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient characterization and suppression methodology of edge effects for leakage current reduction of sub-40nm DRAM device 降低亚40nm DRAM器件漏电流边缘效应的有效表征和抑制方法
2010 International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2010-03-22 DOI: 10.1109/ICMTS.2010.5466864
S. Choi, Y. Park, Chul-Hong Park, Sang Hoon Lee, Moon-Hyun Yoo, Gyu-Tae Kim
{"title":"Efficient characterization and suppression methodology of edge effects for leakage current reduction of sub-40nm DRAM device","authors":"S. Choi, Y. Park, Chul-Hong Park, Sang Hoon Lee, Moon-Hyun Yoo, Gyu-Tae Kim","doi":"10.1109/ICMTS.2010.5466864","DOIUrl":"https://doi.org/10.1109/ICMTS.2010.5466864","url":null,"abstract":"With the process scaling, the leakage current reduction has been the primary design concerns in a nanometer-era VLSI circuit. In this paper, we propose a new lithography process-aware edge effects correction method to reduce the leakage current in the shallow trench isolation (STI). We construct the various test structures to model Ileakage and Ileakage_fringe which represent the leakage currents at the center and edge of the transistor, respectively. The layout near the active edge is modified using the look-up table generated by the calibrated analytic model. On average, the proposed edge effects correction method reduces the leakage current by 18% with the negligible decrease of the drive current at sub-40nm DRAM device.","PeriodicalId":153086,"journal":{"name":"2010 International Conference on Microelectronic Test Structures (ICMTS)","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123391771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Orientation dependence and asymmetry of subthreshold characteristics in CMOSFETs cmosfet中亚阈值特性的方向依赖性和非对称性
2010 International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2010-03-22 DOI: 10.1109/ICMTS.2010.5466854
T. Matsuda, Y. Matsumura, H. Iwata, T. Ohzone
{"title":"Orientation dependence and asymmetry of subthreshold characteristics in CMOSFETs","authors":"T. Matsuda, Y. Matsumura, H. Iwata, T. Ohzone","doi":"10.1109/ICMTS.2010.5466854","DOIUrl":"https://doi.org/10.1109/ICMTS.2010.5466854","url":null,"abstract":"Orientation dependence and asymmetry of V<inf>T</inf> (threshold voltage), g<inf>m</inf> (transconductance), S (subthreshold slope), and I<inf>off</inf> (off-state current at V<inf>G</inf> =3D 0 V) in 0.18 μm n-MOSFETs were measured and analyzed. The test structure contains 8 different channel orientation angles of 0°/45°/90° and three kinds of process conditions. Although V<inf>T</inf>, g<inf>m</inf> and S scarcely show particular anisotropy except for the variation of MOSFET structure and/or impurity profile, the orientation dependence of GIDL characteristics is observed in the wafer with the higher extension dose.","PeriodicalId":153086,"journal":{"name":"2010 International Conference on Microelectronic Test Structures (ICMTS)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115653870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A test structure for statistical evaluation of pn junction leakage current based on CMOS image sensor technology 一种基于CMOS图像传感器技术的pn结漏电流统计评估测试结构
2010 International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2010-03-22 DOI: 10.1109/ICMTS.2010.5466868
K. Abe, T. Fujisawa, Hiroyoshi Suzuki, S. Watabe, R. Kuroda, S. Sugawa, A. Teramoto, T. Ohmi
{"title":"A test structure for statistical evaluation of pn junction leakage current based on CMOS image sensor technology","authors":"K. Abe, T. Fujisawa, Hiroyoshi Suzuki, S. Watabe, R. Kuroda, S. Sugawa, A. Teramoto, T. Ohmi","doi":"10.1109/ICMTS.2010.5466868","DOIUrl":"https://doi.org/10.1109/ICMTS.2010.5466868","url":null,"abstract":"We propose a test structure to enable us to evaluate statistical distributions of small pn junction leakage currents of numerous samples in a very short time (0.1 – 10 fA, 28,672 n+/p diodes in 0.77s). This test structure is based on a CMOS active pixel image sensor, which contains a current-to-voltage conversion function by a capacitor and amplifiers of voltage signals in each pixel. The test structure can be designed easily because of a small number of mask layer requirements (at least one metal layer). Its simplicity has considerable benefits such as an easy fabrication for various processes without exceptional cares and also produces usefulness of statistical evaluation for anomalous pn junction leakage phenomena such as extremely large currents or dynamic and quantum fluctuations which show more and more as the device dimension shrinks.","PeriodicalId":153086,"journal":{"name":"2010 International Conference on Microelectronic Test Structures (ICMTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115365111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Direct probing of trapped charge dynamics in SiN by Kelvin Force Microscopy 开尔文力显微镜直接探测SiN中捕获电荷动力学
2010 International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2010-03-22 DOI: 10.1109/ICMTS.2010.5466851
E. Vianello, E. Nowak, D. Mariolle, N. Chevalier, L. Perniola, G. Molas, J. Colonna, F. Driussi, L. Selmi
{"title":"Direct probing of trapped charge dynamics in SiN by Kelvin Force Microscopy","authors":"E. Vianello, E. Nowak, D. Mariolle, N. Chevalier, L. Perniola, G. Molas, J. Colonna, F. Driussi, L. Selmi","doi":"10.1109/ICMTS.2010.5466851","DOIUrl":"https://doi.org/10.1109/ICMTS.2010.5466851","url":null,"abstract":"In this work, we explore the potential of Kelvin Force Microscopy (KFM) measurements to investigate the lateral charge transport in SiN layers with two different compositions (standard, std, and Silicon rich, Si–rich). The dynamics of the lateral spread of the trapped charge is analyzed with the help of three dimensional numerical device simulations.","PeriodicalId":153086,"journal":{"name":"2010 International Conference on Microelectronic Test Structures (ICMTS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124831342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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