2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献_第2页

Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs 基于硅通孔(TSV)的3D集成电路的电源和旋转感知时钟网络设计

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2010-01-18 DOI: 10.1109/ASPDAC.2010.5419900

Xin Zhao, S. Lim

引用次数: 41

Efficient throughput-guarantees for latency-sensitive networks-on-chip 高效的吞吐量——保证对延迟敏感的片上网络

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2010-01-18 DOI: 10.1109/ASPDAC.2010.5419828

Jonas Diemer, R. Ernst, M. Kauschke

引用次数: 16

Design and chip implementation of an instruction scheduling free ubiquitous processor 指令调度自由泛在处理器的设计与芯片实现

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2010-01-18 DOI: 10.1109/ASPDAC.2010.5419856

M. Fukase, Ryosuke Murakami, Tomoaki Sato

引用次数: 3

Cool and save: Cooling aware dynamic workload scheduling in multi-socket CPU systems 冷却和保存:在多插槽CPU系统中，具有冷却意识的动态工作负载调度

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2010-01-18 DOI: 10.1109/ASPDAC.2010.5419676

R. Ayoub, T. Simunic

引用次数: 11

Floorplanning and topology generation for application-specific Network-on-Chip 面向特定应用的片上网络的平面规划和拓扑生成

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2010-01-18 DOI: 10.1109/ASPDAC.2010.5419825

Bei Yu, Sheqin Dong, Song Chen, S. Goto

引用次数: 45

A3MAP: Architecture-Aware Analytic Mapping for Networks-on-Chip 芯片上网络的体系结构感知分析映射

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2010-01-18 DOI: 10.1145/2209291.2209299

Wooyoung Jang, D. Pan

{"title":"A3MAP: Architecture-Aware Analytic Mapping for Networks-on-Chip","authors":"Wooyoung Jang, D. Pan","doi":"10.1145/2209291.2209299","DOIUrl":"https://doi.org/10.1145/2209291.2209299","url":null,"abstract":"In this paper, we propose a novel and global A3MAP (Architecture-Aware Analytic Mapping) algorithm applied to NoC (Networks-on-Chip) based MPSoC (Multi-Processor System-on-Chip) not only with homogeneous cores on regular mesh architecture as done by most previous mapping algorithms but also with heterogeneous cores on irregular mesh or custom architecture. As a main contribution, we develop a simple yet efficient interconnection matrix that models any task graph and network. Then, task mapping problem is exactly formulated to an MIQP (Mixed Integer Quadratic Programming). Since MIQP is NP-hard [15], we propose two effective heuristics, a successive relaxation algorithm and a genetic algorithm. Experimental results show that A3MAP by the successive relaxation algorithm reduces an amount of traffic up to 5.7%, 16.1% and 7.3% on average in regular mesh, irregular mesh and custom network, respectively, compared to the previous state-of-the-art work [1]. A3MAP by the genetic algorithm reduces more traffic up to 8.8%, 29.4% and 16.1 % on average than [1] in regular mesh, irregular mesh and custom network, respectively even if its runtime is longer.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128899208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 74

Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment 设计时间多v赋值的有老化高阶综合中泄漏功率最小化

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2010-01-18 DOI: 10.1109/ASPDAC.2010.5419799

Yibo Chen, Yuan Xie, Yu Wang, A. Takach

{"title":"Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment","authors":"Yibo Chen, Yuan Xie, Yu Wang, A. Takach","doi":"10.1109/ASPDAC.2010.5419799","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419799","url":null,"abstract":"Aging effects (such as Negative Bias Temperature Instability (NBTI)) can cause the temporal degradation of threshold voltage of transistors, and have become major reliability concerns for deep-submicron (DSM) designs. Meanwhile, leakage power dissipation becomes dominant in total power as technology scales. While multi-threshold voltage assignment has been shown as an effective way to reduce leakage, the NBTI-degradation rates vary with different initial threshold voltage assignment, and therefore motivates the co-optimizations of leakage reduction and NBTI mitigation. This paper minimizes leakage power during high-level synthesis of circuits with bounded delay degradation (thus guaranteed lifetime), using multi-Vth resource libraries. We first propose a fast evaluation approach for NBTI-induced degradation of architectural function units, and multi-Vth resource libraries are built with degradation characterized for each function unit. We then propose an aging-bounded high-level synthesis framework, within which the degraded delays are used to guide the synthesis, and leakage power is optimized through the proposed aging-aware resource rebinding algorithm. Experimental results show that, the proposed techniques can effectively reduce the leakage power with an extra 26% leakage reduction, compared to traditional aging-unaware multi-Vth assignment approach.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"195 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131656807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Improved on-chip router analytical power and area modeling 改进的片上路由器分析能力和区域建模

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2010-01-18 DOI: 10.1109/ASPDAC.2010.5419887

A. Kahng, Bill Lin, K. Samadi

{"title":"Improved on-chip router analytical power and area modeling","authors":"A. Kahng, Bill Lin, K. Samadi","doi":"10.1109/ASPDAC.2010.5419887","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419887","url":null,"abstract":"Over the course of this decade, uniprocessor chips have given way to multi-core chips which have become the primary building blocks of today's computer systems. The presence of multiple cores on a chip shifts the focus from computation to communication as a key bottleneck to achieving performance improvements. As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power has become crucially important. Existing power models (e.g., ORION 2.0 [12], Xpipes [7], etc.) are based on certain router microarchitecture and circuit implementation. Therefore, when validated against different NoC prototypes - different router implementations - we saw significant deviation (up to 40% on average) that can lead to erroneous NoC design choices. This has prompted our development of a new, accurate architecture- and circuit implementation-independent router power and area modeling methodology with complete portability across existing NoC component libraries. Also, validation against a range of implemented router designs confirms substantial improvement in accuracy over existing models.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126629416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 36

Wideband reduced modeling of interconnect circuits by adaptive complex-valued sampling method 基于自适应复值采样方法的互连电路宽带简化建模

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2010-01-18 DOI: 10.1109/ASPDAC.2010.5419924

Hai Wang, S. Tan, Gengsheng Chen

{"title":"Wideband reduced modeling of interconnect circuits by adaptive complex-valued sampling method","authors":"Hai Wang, S. Tan, Gengsheng Chen","doi":"10.1109/ASPDAC.2010.5419924","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419924","url":null,"abstract":"In this paper, we propose a new wideband model order reduction method for interconnect circuits by using a novel adaptive sampling and error estimation scheme. We try to address the outstanding error control problems in the existing sampling-based reduction framework. In the new method, called WBMOR, we explicitly compute the exact residual errors to guide the sampling process. We show that by sampling along the imaginary axis and performing a new complex-valued reduction, the reduced model will match exactly with the original model at the sample points. We show theoretically that the proposed method can achieve the error bound over a given frequency range. Practically the new algorithm can help designers choose the best order of the reduced model for the given frequency range and error bound via adaptive sampling scheme. As a result, it can perform wideband accurate reductions of interconnect circuits for analog and RF applications. We compare several sampling schemes such as linear, logarithmic, and recently proposed re-sampling methods. Experimental results on a number of RLC circuits show that WBMOR is much more accurate than all the other simple sampling methods and the recently proposed re-sampling scheme with the same reduction orders. Compared with the real-valued sampling methods, the complex-valued sampling method is more accurate for the same computational costs.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126338873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

An alternative polychronous model and synthesis methodology for model-driven embedded software 一种用于模型驱动嵌入式软件的多时模型和综合方法

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2010-01-18 DOI: 10.1109/ASPDAC.2010.5419925

B. Jose, S. Shukla

{"title":"An alternative polychronous model and synthesis methodology for model-driven embedded software","authors":"B. Jose, S. Shukla","doi":"10.1109/ASPDAC.2010.5419925","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419925","url":null,"abstract":"Multi-clocked synchronous (a.k.a. Polychronous) specification languages do not assume that execution proceeds by sampling inputs at predetermined global synchronization points. The software synthesized from such specifications are paced by arrival of certain inputs, or evaluation of certain internal variables. Here, we present an alternate polychronous model of computation termed Multi-rate Instantaneous Channel connected Data Flow (MRICDF) actor network model1. Sequential embedded software from MRICDF specifications can be synthesized using epoch analysis, a technique proposed to form a unique order of events without a reference time line. We show how to decide on the implementability of MRICDF specification and how additional epoch information can help in synthesizing deterministic sequential software. The semantics of an MRICDF is akin to that of SIGNAL, but is visual and easier to specify. Also, our prime implicate based epoch analysis technique avoids the complex clock-tree based analysis required in SIGNAL. We experimented with the usability of MRICDF formalism by creating EmCodeSyn, our visual specification and synthesis tool. Our attempt is to make polychronous specification based software synthesis more accessible to engineers, by proposing this alternative model with different semantic exposition and simpler analysis techniques.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126038153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24