NG-RES@HiPEAC最新文献

SDN for Dynamic Reservations on Real-Time Networks (Invited Talk) 面向实时网络动态预留的SDN(特邀演讲)

NG-RES@HiPEAC Pub Date : 2020-01-21 DOI: 10.4230/OASIcs.NG-RES.2020.1

L. Almeida

{"title":"SDN for Dynamic Reservations on Real-Time Networks (Invited Talk)","authors":"L. Almeida","doi":"10.4230/OASIcs.NG-RES.2020.1","DOIUrl":"https://doi.org/10.4230/OASIcs.NG-RES.2020.1","url":null,"abstract":"Recent growing frameworks such as the IoT, IIot, Cloud/Fog/Edge computing, CPS, etc, bring the networking platforms on which they rely to the spotlight, as first class citizens of an increasingly software-dependent landscape. As a result, networks play an increasingly central role in supporting the needed system-wide properties. In particular, we have been working to provide openness and adaptivity together with timeliness guarantees. This combination seems fundamental to support inherently dynamic applications in a resource efficient way, covering not only the cases of systems of systems, systems with variable number of users, components or resources but also systems that undergo frequent live maintenance and even reconfiguration during their lifetime. Examples range from autonomous vehicles to collaborative robotics, remote interactions, fog/edge computing, flexible manufacturing, etc. \u0000We postulate that combining openess and adaptivity with guaranteed timeliness can only be achieved with an adequate communication abstraction supported on adequate protocols. To this end, we have been proposing channel reservation-based communication as a means to provide scalable and open latency-constrained communication and thus enable a more efficient system design. \u0000In this talk we will show our recent work in using Software-Defined Networking (SDN) to provide standard interfaces for traffic flexibility. We proposed extending the SDN OpenFlow protocol with adequate services to take advantage of flexible real-time communication protocols and thus provide standard interfaces for flexible real-time reservations, too. We call it the Real-Time OpenFlow framework (RTOF). We end describing and assessing a prototype implementation based on the HaRTES Ethernet switches.","PeriodicalId":151755,"journal":{"name":"NG-RES@HiPEAC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125452881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Efficient Abstraction of Clock Synchronization at the Operating System Level 操作系统级时钟同步的高效抽象

NG-RES@HiPEAC Pub Date : 1900-01-01 DOI: 10.4230/OASIcs.NG-RES.2023.4

Alessandro Sorrentino, F. Terraneo, A. Leva

引用次数: 1

Can We Trust AI-Powered Real-Time Embedded Systems? (Invited Paper) 我们能信任人工智能驱动的实时嵌入式系统吗?(邀请报告)

NG-RES@HiPEAC Pub Date : 1900-01-01 DOI: 10.4230/OASIcs.NG-RES.2022.1

G. Buttazzo

引用次数: 0

RAVEN: Reinforcement Learning for Generating Verifiable Run-Time Requirement Enforcers for MPSoCs RAVEN:为mpsoc生成可验证的运行时需求执行者的强化学习

NG-RES@HiPEAC Pub Date : 1900-01-01 DOI: 10.4230/OASIcs.NG-RES.2023.7

Khalil Esper, J. Spieck, Pierre-Louis Sixdenier, S. Wildermann, J. Teich

{"title":"RAVEN: Reinforcement Learning for Generating Verifiable Run-Time Requirement Enforcers for MPSoCs","authors":"Khalil Esper, J. Spieck, Pierre-Louis Sixdenier, S. Wildermann, J. Teich","doi":"10.4230/OASIcs.NG-RES.2023.7","DOIUrl":"https://doi.org/10.4230/OASIcs.NG-RES.2023.7","url":null,"abstract":"In embedded systems, applications frequently have to meet non-functional requirements regarding, e.g., real-time or energy consumption constraints, when executing on a given MPSoC target platform. Feedback-based controllers have been proposed that react to transient environmental factors by adapting the DVFS settings or degree of parallelism following some predefined control strategy. However, it is, in general, not possible to give formal guarantees for the obtained controllers to satisfy a given set of non-functional requirements. Run-time requirement enforcement has emerged as a field of research for the enforcement of non-functional requirements at run-time, allowing to define and formally verify properties on respective control strategies specified by automata. However, techniques for the automatic generation of such controllers have not yet been established. In this paper, we propose a technique using reinforcement learning to automatically generate verifiable feedback-based enforcers. For that, we train a control policy based on a representative input sequence at design time. The learned control strategy is then transformed into a verifiable enforcement automaton which constitutes our run-time control model that can handle unseen input data. As a case study, we apply the approach to generate controllers that are able to increase the probability of satisfying a given set of requirement verification goals compared to multiple state-of-the-art approaches, as can be verified by model checkers.","PeriodicalId":151755,"journal":{"name":"NG-RES@HiPEAC","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125663178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Static Allocation of Basic Blocks Based on Runtime and Memory Requirements in Embedded Real-Time Systems with Hierarchical Memory Layout 基于分层内存布局嵌入式实时系统运行时和内存需求的基本块静态分配

NG-RES@HiPEAC Pub Date : 1900-01-01 DOI: 10.4230/OASIcs.NG-RES.2021.3

Philipp Jungklass, Mladen Berekovic

{"title":"Static Allocation of Basic Blocks Based on Runtime and Memory Requirements in Embedded Real-Time Systems with Hierarchical Memory Layout","authors":"Philipp Jungklass, Mladen Berekovic","doi":"10.4230/OASIcs.NG-RES.2021.3","DOIUrl":"https://doi.org/10.4230/OASIcs.NG-RES.2021.3","url":null,"abstract":"Modern microcontrollers for safety-critical real-time systems use a hierarchical memory system to increase execution speed and memory capacity. For this purpose, flash memories, which offer high capacity at low transfer rates, are combined with scratchpad memories, which provide high access speed at low memory capacities. The main goal is to use both types of memory in such a way that their advantages are optimally exploited. The target is to allocate runtime-intensive code fragments with low memory requirements to the fast scratchpad memories. Previous approaches to separate program code on system memories consider the executed functions as the smallest logical unit. This is contradicted by the fact that not all parts of a function have the same computing time in relation to their memory usage. This article introduces a procedure that automatically analyses the compiled source code and identifies runtime intensive fragments. For this purpose, the translated code is executed in an offline simulator and the maximum repetition for each instruction is detected. This information is used to create logical code fragments called basic blocks. This is repeated for all functions in the overall system. During the analysis of the functions, the dependencies between them are also extracted and a corresponding call-graph with the call frequencies is generated. By combining the information from the call graph and the evaluation of the basic blocks, a prognosis of the computing load of the respective code blocks is created, which serves as base for the distribution into the fast scratchpad memories. To verify the described procedure, EEMBC’s CoreMark is executed on an Infineon AURIX TC29x microcontroller, in which different scratchpad sizes are simulated. It is demonstrated that the allocation of basic blocks scales significantly better with smaller memory sizes than the previous function-based approach. 2012 ACM Subject Classification Computer systems organization → Real-time system architecture","PeriodicalId":151755,"journal":{"name":"NG-RES@HiPEAC","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131113713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Ahead-Of-Real-Time (ART): A Methodology for Static Reduction of Worst-Case Execution Time 超前实时(ART):静态减少最坏情况执行时间的方法

NG-RES@HiPEAC Pub Date : 1900-01-01 DOI: 10.4230/OASIcs.NG-RES.2022.4

Daniele Cattaneo, Gabriele Magnani, Stefano Cherubin, G. Agosta

{"title":"Ahead-Of-Real-Time (ART): A Methodology for Static Reduction of Worst-Case Execution Time","authors":"Daniele Cattaneo, Gabriele Magnani, Stefano Cherubin, G. Agosta","doi":"10.4230/OASIcs.NG-RES.2022.4","DOIUrl":"https://doi.org/10.4230/OASIcs.NG-RES.2022.4","url":null,"abstract":"Precision tuning is an approximate computing technique for trading precision with lower execution time, and it has been increasingly important in embedded and high-performance computing applications. In particular, embedded applications benefit from lower precision in order to reduce or remove the dependency on computationally-expensive data types such as floating point. Amongst such applications, an important fraction are mission-critical tasks, such as control systems for vehicles or medical use-cases. In this context, the usefulness of precision tuning is limited by concerns about verificability of real-time and quality-of-service constraints. However, with the introduction of optimisations techniques based on integer linear programming and rigorous WCET (Worst-Case Execution Time) models, these constraints not only can be verified automatically, but it becomes possible to use precision tuning to automatically enforce these constraints even when not previously possible. In this work, we show how to combine precision tuning with WCET analysis to enforce a limit on the execution time by using a constraint-based code optimisation pass with a state-of-the-art precision tuning framework.","PeriodicalId":151755,"journal":{"name":"NG-RES@HiPEAC","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122200496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks Using Multi-Reader Buffers 使用多读卡器缓冲的数据流网络并行实现的吞吐量和内存优化

NG-RES@HiPEAC Pub Date : 1900-01-01 DOI: 10.4230/OASIcs.NG-RES.2023.6

Martín Letras, J. Falk, Jürgen Teich

{"title":"Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks Using Multi-Reader Buffers","authors":"Martín Letras, J. Falk, Jürgen Teich","doi":"10.4230/OASIcs.NG-RES.2023.6","DOIUrl":"https://doi.org/10.4230/OASIcs.NG-RES.2023.6","url":null,"abstract":"In this paper, we introduce the concept of Multi-Reader Buffers (MRBs) for high throughput and memory-efficient implementation of dataflow applications. Our work is motivated by the huge amount of data that needs to be processed and typically accessed in a FIFO manner, particularly in image and video processing applications. Here, multi-cast, fork, and merge operator implementations known today produce huge memory overheads by storing and communicating copies of the same data. As a remedy, we first introduce MRBs as buffers preserving FIFO semantics for a finite number of readers of the same data while storing each data item only once. Second, we present an approach for memory minimization of data flow networks by replacing all multi-cast actors and connected FIFOs with MRBs. Third, we present a Design Space Exploration approach to selectively replace multi-cast actors with MRBs in order to explore memory, throughput, and processor resource allocation tradeoffs. Our results show that the explored Pareto fronts of our approach improve the solution quality over a reference by 78 % in average for six benchmark applications in terms of a hypervolume indicator","PeriodicalId":151755,"journal":{"name":"NG-RES@HiPEAC","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134298092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Control Systems in the Presence of Computational Problems (Invited Talk) 存在计算问题的控制系统(特邀演讲)

NG-RES@HiPEAC Pub Date : 1900-01-01 DOI: 10.4230/OASIcs.NG-RES.2023.1

M. Maggio

{"title":"Control Systems in the Presence of Computational Problems (Invited Talk)","authors":"M. Maggio","doi":"10.4230/OASIcs.NG-RES.2023.1","DOIUrl":"https://doi.org/10.4230/OASIcs.NG-RES.2023.1","url":null,"abstract":"Feedback control is a central enabling technology in a wide range of applications. Control systems are at the core of energy distribution infrastructure, regulate the behaviour of engines in vehicles, and are embedded in household appliances like washing machines. Control is centred around the feedback mechanism. Sensors provide information about the current state of the physical environment. This is used to compute suitable control actions to fulfil performance requirements, that are then implemented by actuators. For example, adaptive cruise control systems use measurements from a range of sensors to determine how to adjust the throttle to automatically regulate the vehicle’s speed, while maintaining a safe distance from vehicles ahead. Control actions are often calculated using hardware and software. Hence, the computation of the new control signals is subject to accidental faults, systematic issues, and software bugs. In practice, these computational problems are often ignored. But when can this be done safely? This talk will introduce a framework for analyzing the behaviour of control software subject to computational problems. The focus will be on the development of tools that can certify when control software is able to fulfil the system requirements, despite the presence of computational problems. 2012 ACM","PeriodicalId":151755,"journal":{"name":"NG-RES@HiPEAC","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124683558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Bao: A Lightweight Static Partitioning Hypervisor for Modern Multi-Core Embedded Systems 现代多核嵌入式系统的轻量级静态分区管理程序

NG-RES@HiPEAC Pub Date : 1900-01-01 DOI: 10.4230/OASIcs.NG-RES.2020.3

José Martins, A. Tavares, M. Solieri, M. Bertogna, S. Pinto

引用次数: 58

A Low Energy FPGA Platform for Real-Time Event-Based Control 基于事件实时控制的低功耗FPGA平台

NG-RES@HiPEAC Pub Date : 1900-01-01 DOI: 10.4230/OASIcs.NG-RES.2020.4

Silvano Seva, Claudia Esther Lukaschewsky Mauriziano, W. Fornaciari, A. Leva

引用次数: 2