Static Allocation of Basic Blocks Based on Runtime and Memory Requirements in Embedded Real-Time Systems with Hierarchical Memory Layout

Philipp Jungklass, Mladen Berekovic
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引用次数: 2

Abstract

Modern microcontrollers for safety-critical real-time systems use a hierarchical memory system to increase execution speed and memory capacity. For this purpose, flash memories, which offer high capacity at low transfer rates, are combined with scratchpad memories, which provide high access speed at low memory capacities. The main goal is to use both types of memory in such a way that their advantages are optimally exploited. The target is to allocate runtime-intensive code fragments with low memory requirements to the fast scratchpad memories. Previous approaches to separate program code on system memories consider the executed functions as the smallest logical unit. This is contradicted by the fact that not all parts of a function have the same computing time in relation to their memory usage. This article introduces a procedure that automatically analyses the compiled source code and identifies runtime intensive fragments. For this purpose, the translated code is executed in an offline simulator and the maximum repetition for each instruction is detected. This information is used to create logical code fragments called basic blocks. This is repeated for all functions in the overall system. During the analysis of the functions, the dependencies between them are also extracted and a corresponding call-graph with the call frequencies is generated. By combining the information from the call graph and the evaluation of the basic blocks, a prognosis of the computing load of the respective code blocks is created, which serves as base for the distribution into the fast scratchpad memories. To verify the described procedure, EEMBC’s CoreMark is executed on an Infineon AURIX TC29x microcontroller, in which different scratchpad sizes are simulated. It is demonstrated that the allocation of basic blocks scales significantly better with smaller memory sizes than the previous function-based approach. 2012 ACM Subject Classification Computer systems organization → Real-time system architecture
基于分层内存布局嵌入式实时系统运行时和内存需求的基本块静态分配
用于安全关键实时系统的现代微控制器使用分层内存系统来提高执行速度和内存容量。为此,闪存在低传输速率下提供高容量,与刮刮板存储器相结合,后者在低存储容量下提供高访问速度。我们的主要目标是以最佳的方式使用这两种类型的内存,以充分利用它们的优势。目标是将具有低内存需求的运行时密集型代码片段分配到快速的刮擦板内存中。以前在系统内存中分离程序代码的方法将执行的函数视为最小的逻辑单元。与此相矛盾的是,并非函数的所有部分都具有与内存使用相关的相同计算时间。本文介绍了一个自动分析编译后的源代码并识别运行时密集型片段的过程。为此,翻译后的代码在脱机模拟器中执行,并检测每个指令的最大重复次数。该信息用于创建称为基本块的逻辑代码片段。整个系统的所有功能都是重复的。在分析函数的过程中,还提取了它们之间的依赖关系,并生成了包含调用频率的相应调用图。通过结合调用图的信息和基本块的评估,对各个代码块的计算负荷进行预测,并以此为基础将其分配到快速刮记板存储器中。为了验证所描述的过程,EEMBC的CoreMark在英飞凌AURIX TC29x微控制器上执行,其中模拟了不同尺寸的刮记板。结果表明,与之前基于函数的方法相比,在更小的内存大小下,基本块的分配明显更好。2012 ACM学科分类计算机系统组织→实时系统架构
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