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2010 IEEE International Memory Workshop最新文献

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A phenomenological model of oxygen ion transport for metal oxide resistive switching memory 金属氧化物阻性开关存储器中氧离子输运的现象学模型
2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488321
Shimeng Yu, H. Wong
{"title":"A phenomenological model of oxygen ion transport for metal oxide resistive switching memory","authors":"Shimeng Yu, H. Wong","doi":"10.1109/IMW.2010.5488321","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488321","url":null,"abstract":"Reproducible resistance switching phenomenon in metal oxides is attributed to the non-linear oxygen ions transport. Here we present a phenomenological model to provide a unified explanation for both the unipolar and bipolar resistive switching mechanism. Numerical simulation results reveal the switching mode is determined by the electrode/oxide interface property. Without/with an interfacial barrier, unipolar/bipolar switching behavior is obtained. Also, the voltage-time dilemma between fast switching and long retention is explained by the non-linearity of the ionic transport under high electric field. Experimental data are employed for model verification.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132323774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 40nm low power SRAM retention circuit with PVT-aware self-refreshing virtual VDD regulation 40nm低功耗SRAM保持电路，具有pvt感知自刷新虚拟VDD调节
2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488323
C. Dray, N. Badereddine, C. Chanussot
{"title":"A 40nm low power SRAM retention circuit with PVT-aware self-refreshing virtual VDD regulation","authors":"C. Dray, N. Badereddine, C. Chanussot","doi":"10.1109/IMW.2010.5488323","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488323","url":null,"abstract":"This paper describes an integrated SRAM standby power reduction design in a 40nm low power process. It features a closed-loop array leakage control with floating bitlines, reducing 46% of leakage current. It relies on self-refreshing virtual VDD clocked by a PVT-compensated SRAM worst-case data retention sensor. The concept is implemented in a 256kbit SRAM with a 0.242µm2 6T cell.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129506276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Improved resistive switching memory characteristics using novel bi-layered Ge0.2Se0.8/Ta2O5 solid-electrolytes 利用新型双层Ge0.2Se0.8/Ta2O5固体电解质改善电阻开关记忆特性
2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488314
S. Z. Rahaman, S. Maikap
{"title":"Improved resistive switching memory characteristics using novel bi-layered Ge0.2Se0.8/Ta2O5 solid-electrolytes","authors":"S. Z. Rahaman, S. Maikap","doi":"10.1109/IMW.2010.5488314","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488314","url":null,"abstract":"Novel bi-layered solid electrolytic based resistive switching memory device using Al/Cu/Ge<inf>0.2</inf>Se<inf>0.8</inf>/Ta<inf>2</inf>O<inf>5</inf>/W structure has been investigated for the first time. The tight distribution of resistance states and threshold voltage are achieved as compared to that of single layer Ge<inf>0.2</inf>Se<inf>0.8</inf> solid-electrolyte. Stable endurance of ≫3.5×10<sup>5</sup> cycles and excellent retention characteristics with a low compliance current of 100 nA are obtained at 85°C. The high resistance state (R<inf>High</inf>) increases with decreasing the device size from 8 µm to 0.2 µm. The low resistance state (R<inf>Low</inf>) is independent with different via diameters. The R<inf>Low</inf> decreases with increasing the compliance currents from 1nA to 1mA, which can be useful for future nanoscale low power consuming nonvolatile memory device applications.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134546976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A critical examination of 3D stackable NAND Flash memory architectures by simulation study of the scaling capability 通过对缩放能力的模拟研究，对3D可堆叠NAND闪存架构进行了关键检查
2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488390
Y. Hsiao, H. Lue, T. Hsu, K. Hsieh, Chih-Yuan Lu
{"title":"A critical examination of 3D stackable NAND Flash memory architectures by simulation study of the scaling capability","authors":"Y. Hsiao, H. Lue, T. Hsu, K. Hsieh, Chih-Yuan Lu","doi":"10.1109/IMW.2010.5488390","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488390","url":null,"abstract":"Various 3D NAND Flash array architectures including P-BiCS, TCAT, VSAT, and VG are critically examined in this work by extensive 3D TCAD simulations. All structures have X,Y lateral scaling limitation since the minimal ONO thickness (∼20 nm) and poly channel thickness (∼10nm) can not be scaled further. Among them VG may have the best X-direction scalability to F∼2X nm node, and no penalty of increasing Z layer number since the channel current flows horizontally. We propose a buried-channel junction-free NAND to improve the read current for all 3D NAND arrays and our simulation results well support this structure. For the first time, “Z-interference” in 3D NAND Flash is examined and it indicates a new Z-direction scaling limitation. The present work is of crucial importance in understanding various 3D NAND Flash approaches.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133337963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
A consistent explanation of the role of the SiN composition on the program/retention characteristics of MANOS and NROM like memories 关于SiN组成对MANOS和NROM类存储器的程序/保留特性的作用的一致解释
2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488384
E. Vianello, E. Nowak, L. Perniola, F. Driussi, P. Blaise, G. Molas, B. De Salvo, L. Selmi
{"title":"A consistent explanation of the role of the SiN composition on the program/retention characteristics of MANOS and NROM like memories","authors":"E. Vianello, E. Nowak, L. Perniola, F. Driussi, P. Blaise, G. Molas, B. De Salvo, L. Selmi","doi":"10.1109/IMW.2010.5488384","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488384","url":null,"abstract":"In this work, we show that a detailed atomistic model of SiN defects provides a consistent explanation of the program/erase/retention characteristics of both NROM and MANOS charge-trap cells. Our analysis of devices with SiN layers of different stoichiometry is also consistent with original KFM measurements of trapped charge drift in SiN layers.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131904724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Demonstration of Conductive Bridging Random Access Memory (CBRAM) in Logic CMOS Process 导电桥接随机存取存储器(CBRAM)在逻辑CMOS工艺中的演示
2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488320
C. Gopalan, Y. Ma, T. Gallo, Janet Wang, E. Runnion, J. Sáenz, F. Koushan, S. Hollmer
{"title":"Demonstration of Conductive Bridging Random Access Memory (CBRAM) in Logic CMOS Process","authors":"C. Gopalan, Y. Ma, T. Gallo, Janet Wang, E. Runnion, J. Sáenz, F. Koushan, S. Hollmer","doi":"10.1109/IMW.2010.5488320","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488320","url":null,"abstract":"Today's main stream NVM technologies require operational conditions that are incompatible with modern low voltage logic CMOS designs. This characteristic results in complex integration issues as well as costly process and array concept especially for embedded NVM use models. Conductive bridging memory cell (CBRAM) technology is an attractive emerging memory technology that offers simple integration and scalable operational conditions. These unique features make CBRAM technology an ideal candidate for embedded applications. In this paper, we have shown successful integration of CBRAM into Copper and Aluminum back end logic CMOS processes with minimal number of added masks.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127848433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 124
Future evolution of memory subsystem in mobile applications 移动应用中内存子系统的未来发展
2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488396
Youngjoon Choi, Hyo-Moon Jeong, Hyunbo Kim
{"title":"Future evolution of memory subsystem in mobile applications","authors":"Youngjoon Choi, Hyo-Moon Jeong, Hyunbo Kim","doi":"10.1109/IMW.2010.5488396","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488396","url":null,"abstract":"As smart phones make for the focal point of today's ubiquitous computing, demands of increased memory performance for DRAM and Flash storage are surging while trying to suppress power consumption. New DRAM architectures such as Wide IO, serial I/O and combo are investigated in the industry. Fast read/write access to Flash storage is needed with the virtual memory system under multi-tasking. This paper discusses new DRAM architectures from the perspective of performance, power consumption, pin counts and others. The performance enhancement of Flash storage is discussed in optimizing the internal device for the system access pattern, and on the requirements of system software and storage interface scheme for dealing with multiple access queues.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121342815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A novel fatigue-insensitive self-referenced scheme for 1T1C FRAM 一种新的1T1C FRAM疲劳不敏感自参考方案
2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488402
Ze Jia, Gong Zhang, Ming-ming Zhang, T. Ren, Hong-yi Chen
{"title":"A novel fatigue-insensitive self-referenced scheme for 1T1C FRAM","authors":"Ze Jia, Gong Zhang, Ming-ming Zhang, T. Ren, Hong-yi Chen","doi":"10.1109/IMW.2010.5488402","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488402","url":null,"abstract":"A novel self-referenced scheme without reference cell is proposed for 1T1C FRAM, which is a new solution to the access scheme for high density FRAM. It is insensitive and robust to fatigue of the FRAM cells and can overcome the challenges on reference signal design for 1T1C FRAM. Furthermore, the proposed scheme can decrease the power consumption and the die size of 1T1C FRAM, compared with conventional schemes.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126974394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
The 3-dimensional vertical FG NAND flash memory cell arrays with the novel electrical S/D technique using the Extended Sidewall Control Gate (ESCG) 采用扩展侧壁控制门(ESCG)的新型电子S/D技术的三维垂直FG NAND闪存单元阵列
2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488392
M. Seo, Sung-Kye Park, T. Endoh
{"title":"The 3-dimensional vertical FG NAND flash memory cell arrays with the novel electrical S/D technique using the Extended Sidewall Control Gate (ESCG)","authors":"M. Seo, Sung-Kye Park, T. Endoh","doi":"10.1109/IMW.2010.5488392","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488392","url":null,"abstract":"We propose the novel 3-dimensional (3-D) vertical floating gate (FG) NAND flash memory cell arrays with novel electrical source/drain (S/D) technique using Extended Sidewall Control Gate (ESCG). Cylindrical FG structure cell is implemented to overcome the reliability issues of the charge trap cell such as SONOS and TANOS cell. We also propose the novel electrical S/D layer using the ESCG structure to realize the enhancement mode operation. Using this novel structure, we successfully demonstrate the normal flash cell operation with high-speed programming and superior read current due to both the increasing of coupling ratio and low resistive electrical S/D technique. Moreover, we found that the 3-D vertical flash memory cell array with novel electrical S/D technique had less interference with neighboring cells by about 50% in comparison with planar FG NAND cell. From above all, the proposed cell array is one of the candidates of Terabit 3-D vertical NAND flash cell array with high-speed read/program operation and high reliability.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125062429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Exploration of rare earth materials for future interpoly dielectric replacement in Flash memory devices 在快闪记忆体装置中，未来内插电介质替代之稀土材料之探索
2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488331
D. Wellekens, S. Van Elshocht, C. Adelmann, J. Meersschaut, J. Swerts, J. Kittl, A. Cacciato, I. Debusschere, M. Jurczak, J. van Houdt
{"title":"Exploration of rare earth materials for future interpoly dielectric replacement in Flash memory devices","authors":"D. Wellekens, S. Van Elshocht, C. Adelmann, J. Meersschaut, J. Swerts, J. Kittl, A. Cacciato, I. Debusschere, M. Jurczak, J. van Houdt","doi":"10.1109/IMW.2010.5488331","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488331","url":null,"abstract":"Rare-earth lanthanates and scandates have been studied for possible use as future Flash interpoly dielectrics. It was shown that a post-deposition anneal in O2 at high temperature (∼1000°C or above) gives rise to silicate formation. This results in excellent memory retention and larger robustness of the layers as compared to anneal in N2.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115230842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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