2017 7th International Symposium on Embedded Computing and System Design (ISED)最新文献_第2页

CIFR: A complete in-place fault remapping strategy for CMP cache using dynamic reuse distance 一个使用动态重用距离的CMP缓存的完整的就地故障重映射策略

2017 7th International Symposium on Embedded Computing and System Design (ISED) Pub Date : 2017-12-01 DOI: 10.1109/ISED.2017.8303922

A. Choudhury, B. Sikdar

{"title":"CIFR: A complete in-place fault remapping strategy for CMP cache using dynamic reuse distance","authors":"A. Choudhury, B. Sikdar","doi":"10.1109/ISED.2017.8303922","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303922","url":null,"abstract":"Dynamic voltage and frequency scaling puts threats to reliability in Chip Multiprocessors (CMPs). Cache being the most susceptible to faults, the fault tolerance techniques are necessary to ensure error free execution even if there are faults in cache. Existing fault tolerance techniques lack completeness in fault protection as well as harm effective capacity of the cache. They either remap faulty blocks to non-conflicting faulty blocks or use some auxiliary cache. This work proposes a fault remapping strategy that ensures completeness in fault protection without affecting the effective capacity of the Last Level Cache by remapping all effective faulty cache lines to either non-conflicting faulty cache lines or low-reusable healthy lines. The reusability is predicted using dynamic reuse distance analysis and cache lines are ranked by their protecting distance. Only the highly reusable faulty lines are considered for remapping to low reusable non-conflicting faulty lines. Failing that the low-reusable healthy lines are considered as the target and this avoids the requirement of any auxiliary cache. Cycle accurate simulation in Multi2Sim 5.0 with plethora of fault maps, in an octacore CMP architecture, reveals up to 38.73% increase in hit ratio over the existing fault remapping techniques.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125172906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Design and implementation of PID controller based on orthogonal wavelet filter-banks in FPGA 基于正交小波滤波器组的PID控制器的设计与实现

2017 7th International Symposium on Embedded Computing and System Design (ISED) Pub Date : 2017-12-01 DOI: 10.1109/ISED.2017.8303928

Priyanandini Das, Pranose J. Edavoor, S. Raveendran, Sunil Rathore, A. Rahulkar

引用次数: 0

Effect of optimal allocation of multiple DG and D-STATCOM in radial distribution system for minimizing losses and THD 径向配电系统中多DG和D-STATCOM优化配置对最大损耗和最小THD的影响

2017 7th International Symposium on Embedded Computing and System Design (ISED) Pub Date : 2017-12-01 DOI: 10.1109/ISED.2017.8303936

A. Gupta

引用次数: 16

Design of an all-digital, low power time-to-digital converter in 0.18μm CMOS 基于0.18μm CMOS的全数字低功耗时数转换器设计

2017 7th International Symposium on Embedded Computing and System Design (ISED) Pub Date : 2017-12-01 DOI: 10.1109/ISED.2017.8303944

Ankur Pokhara, Jatin Agrawal, B. Mishra

引用次数: 7

Application of variational mode decomposition and ABC optimized DAG-SVM in arrhythmia analysis 变分模态分解与ABC优化的DAG-SVM在心律失常分析中的应用

2017 7th International Symposium on Embedded Computing and System Design (ISED) Pub Date : 2017-12-01 DOI: 10.1109/ISED.2017.8303935

S. Raj, K. C. Ray

{"title":"Application of variational mode decomposition and ABC optimized DAG-SVM in arrhythmia analysis","authors":"S. Raj, K. C. Ray","doi":"10.1109/ISED.2017.8303935","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303935","url":null,"abstract":"Automatic analysis of long-term electrocardiogram (ECG) recordings is crucial for timely and accurate diagnosis of life-threatening cardiovascular diseases. This article presents an efficient ECG classification scheme using variational mode decomposition approach. The method decomposes a time-domain input signal into various variational mode functions (VMFs). The VMD method adaptively decomposes an input signal into a number of modes to estimate their center frequencies, so that the band-limited modes can regenerate the input signal exactly. In this study, only mode-2 (M2) is used as morphological features and represented in reduced dimensions by employing principal component analysis (PCA). Further, the dynamic features (RR-intervals) are concatenated to constitute a feature set representing each heartbeat. The PCA method is employed to balance the impact of both the features exhibiting two different characteristics of an heartbeat i.e within the event and among the events. These extracted features of each heartbeat are further utilized for recognition into one of 16 heartbeat classes using artificial bee colony (ABC) optimized directed acyclic graph support vector machines (DAG-SVM). The proposed method is evaluated on the benchmark MIT-BIH arrhythmia database yielding an improved accuracy, sensitivity, positive predictivity and F-score of 98.72%, 98.72% and 98.72% respectively over the methodologies available in literature to the state-of-art diagnosis.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114532025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

A double trench 4H — SiC MOSFET as an enhanced model of SiC UMOSFET 双沟槽4H - SiC MOSFET作为SiC MOSFET的增强模型

2017 7th International Symposium on Embedded Computing and System Design (ISED) Pub Date : 2017-12-01 DOI: 10.1109/ISED.2017.8303939

Alisha Oraon, Shradha Shreya, Renuka Kumari, A. Islam

引用次数: 2

An approach for area and power optimization of flipping 3-D discrete wavelet transform architecture 一种翻转三维离散小波变换结构的面积和功耗优化方法

2017 7th International Symposium on Embedded Computing and System Design (ISED) Pub Date : 2017-12-01 DOI: 10.1109/ISED.2017.8303941

G. Hegde, K. S. Reddy, T. K. Ramesh

引用次数: 2

Implementation of adaptive image compression algorithm using varying bit-length daubechies wavelet coefficient with three-level encryption on Zynq 7000 在zynq7000上采用变位长多波系数和三级加密实现自适应图像压缩算法

2017 7th International Symposium on Embedded Computing and System Design (ISED) Pub Date : 2017-12-01 DOI: 10.1109/ISED.2017.8303927

Pranose J. Edavoor, S. Raveendran, A. Rahulkar

引用次数: 2

Towards lightweight satisfiability solvers for self-verification 面向自我验证的轻量级满意度求解器

2017 7th International Symposium on Embedded Computing and System Design (ISED) Pub Date : 2017-12-01 DOI: 10.1109/ISED.2017.8303924

Fritjof Bornebusch, R. Wille, R. Drechsler

{"title":"Towards lightweight satisfiability solvers for self-verification","authors":"Fritjof Bornebusch, R. Wille, R. Drechsler","doi":"10.1109/ISED.2017.8303924","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303924","url":null,"abstract":"Solvers for Boolean satisfiability (SAT solvers) are essential for various hardware and software verification tasks such as equivalence checking, property checking, coverage analysis, etc. Nevertheless, despite the fact that very powerful solvers have been developed in the recent decades, this progress often still cannot cope with the exponentially increasing complexity of those verification tasks. As a consequence, researchers and engineers are investigating complementarily different verification approaches which require changes in the core methods as well. Self-verification is such a promising approach where e.g. SAT solvers have to be executed on the system itself. This comes with hardware restrictions such as limited memory and motivates lightweight SAT solvers. This work provides a case study towards the development of such solvers. To this end, we consider several core techniques of SAT solvers (such as clause learning, Boolean constraint propagation, etc.) and discuss as well as evaluate how they contribute to both, the run-time performance but also the required memory requirements. The findings from this case study provide a basis for the development of dedicated, i.e. lightweight, SAT solvers to be used in self-verification solutions.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130415811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Multirotor performance optimization using genetic algorithm 基于遗传算法的多转子性能优化

2017 7th International Symposium on Embedded Computing and System Design (ISED) Pub Date : 2017-12-01 DOI: 10.1109/ISED.2017.8303947

Umang Agarwal

引用次数: 1