{"title":"基于0.18μm CMOS的全数字低功耗时数转换器设计","authors":"Ankur Pokhara, Jatin Agrawal, B. Mishra","doi":"10.1109/ISED.2017.8303944","DOIUrl":null,"url":null,"abstract":"A full custom, all digital, low power Time-to-Digital Converter (TDC) is proposed. The proposed architecture contains a 20-bit ripple counter, an encoder, an edge detector and a Ring Delay Line (RDL). The TDC core, has an active area of 0.026mm2 implemented in 0.18µm CMOS technology that achieves a resolution of 586.4ps/LSB and 201.8ps/LSB, lower power consumption of 32.5µW and 315.5µW, with the distance calculation up to 2949.4km and 1015.7km at 1V and 1.8V respectively, making it feasible for time-of-flight measurement in space applications.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Design of an all-digital, low power time-to-digital converter in 0.18μm CMOS\",\"authors\":\"Ankur Pokhara, Jatin Agrawal, B. Mishra\",\"doi\":\"10.1109/ISED.2017.8303944\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A full custom, all digital, low power Time-to-Digital Converter (TDC) is proposed. The proposed architecture contains a 20-bit ripple counter, an encoder, an edge detector and a Ring Delay Line (RDL). The TDC core, has an active area of 0.026mm2 implemented in 0.18µm CMOS technology that achieves a resolution of 586.4ps/LSB and 201.8ps/LSB, lower power consumption of 32.5µW and 315.5µW, with the distance calculation up to 2949.4km and 1015.7km at 1V and 1.8V respectively, making it feasible for time-of-flight measurement in space applications.\",\"PeriodicalId\":147019,\"journal\":{\"name\":\"2017 7th International Symposium on Embedded Computing and System Design (ISED)\",\"volume\":\"54 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 7th International Symposium on Embedded Computing and System Design (ISED)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISED.2017.8303944\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISED.2017.8303944","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of an all-digital, low power time-to-digital converter in 0.18μm CMOS
A full custom, all digital, low power Time-to-Digital Converter (TDC) is proposed. The proposed architecture contains a 20-bit ripple counter, an encoder, an edge detector and a Ring Delay Line (RDL). The TDC core, has an active area of 0.026mm2 implemented in 0.18µm CMOS technology that achieves a resolution of 586.4ps/LSB and 201.8ps/LSB, lower power consumption of 32.5µW and 315.5µW, with the distance calculation up to 2949.4km and 1015.7km at 1V and 1.8V respectively, making it feasible for time-of-flight measurement in space applications.
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