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2017 7th International Symposium on Embedded Computing and System Design (ISED)最新文献

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Performance analysis of virtualized embedded computing systems 虚拟嵌入式计算系统的性能分析
2017 7th International Symposium on Embedded Computing and System Design (ISED) Pub Date : 2017-12-01 DOI: 10.1109/ISED.2017.8303932
D. Mathew, B. Jose
{"title":"Performance analysis of virtualized embedded computing systems","authors":"D. Mathew, B. Jose","doi":"10.1109/ISED.2017.8303932","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303932","url":null,"abstract":"Virtualization has provided flexibility on a wide range of platforms such as high performance servers to personal computers. Naturaly the next frontier is embedded systems. Even though embedded devices have many resource limitations, virtualization offers advantages such as isolation and security. This paper briefly describes three among the different virtualization approaches for embedded systems. The goal is to understand the performance characteristics of various virtualization types. A benchmarking tool is used to measure the processor performance. The chosen approaches are of microkernel or hypervisor category. The first one is QEMU which is a Type 2 hypervisor and the second one is a microkernel based approach. The third one is a Type 1 Xen hypervisor. The performance measurement is done using QEMU and it is compared with numbers obtained from some of the popular embedded devices. Our observations regarding hypervisor performance are discussed to form conclusions on why some of the virtualization features are important.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131410719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
OTORNoC: Optical tree of rings network on chip for 1000 core systems OTORNoC:用于1000核系统的片上环网光树
2017 7th International Symposium on Embedded Computing and System Design (ISED) Pub Date : 2017-12-01 DOI: 10.1109/ISED.2017.8303940
Soumyajit Poddar, Suraj, Amit Kumar Yadav, H. Rahaman
{"title":"OTORNoC: Optical tree of rings network on chip for 1000 core systems","authors":"Soumyajit Poddar, Suraj, Amit Kumar Yadav, H. Rahaman","doi":"10.1109/ISED.2017.8303940","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303940","url":null,"abstract":"Optical Networks on Chip are an emerging communication platform for high performance multi core systems on chip. In this work a novel thousand core topology is proposed that increases optical link utilization and scales up bandwidth to enable single chip TeraFlops performance. Performance benefits of about 1.8× and 3× reduction in optical power is obtained over the existing state of the art multicore chips.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114237175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A secure partial encryption scheme based on bit plane manipulation 一种基于位平面操作的安全部分加密方案
2017 7th International Symposium on Embedded Computing and System Design (ISED) Pub Date : 2017-12-01 DOI: 10.1109/ISED.2017.8303925
Bhaskar Mondal, T. Mandal, P. Kumar, Neel Biswas
{"title":"A secure partial encryption scheme based on bit plane manipulation","authors":"Bhaskar Mondal, T. Mandal, P. Kumar, Neel Biswas","doi":"10.1109/ISED.2017.8303925","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303925","url":null,"abstract":"With the increasing volume of digital information the cost of encryption is also increasing as conventionally the whole information is encrypted. But it is possible to provide equal security by partially encrypting the information, which will reduce the computation cost. In this paper authors proposed a partial encryption scheme based on bit plane manipulation. The proposed scheme encrypts only those bits which carry significant amount of information instead the whole image. The scheme uses DNA computation and chaotic henon map which are run on low computational overhead. Therefore, the scheme runs on low computational overhead. Moreover, the values of UACI and NPCR of the partially encrypted image is better than that of AES and some other schemes.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123986902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A self-bandwidth switching & area-efficient PLL using multiplexer-controlled frequency selector 一种使用多路器控制频率选择器的自带宽开关和面积高效锁相环
2017 7th International Symposium on Embedded Computing and System Design (ISED) Pub Date : 2017-12-01 DOI: 10.1109/ISED.2017.8303919
B. Kumar, S. Pandey, Puneet Arora, R. Shrestha
{"title":"A self-bandwidth switching & area-efficient PLL using multiplexer-controlled frequency selector","authors":"B. Kumar, S. Pandey, Puneet Arora, R. Shrestha","doi":"10.1109/ISED.2017.8303919","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303919","url":null,"abstract":"In this paper, we propose a new multiplexer-based frequency selector for designing area-efficient phase locked loop (PLL) for frequency synthesis. Such reduction in the design area has been achieved by replacing conventional capacitor array in voltage controlled oscillator of this PLL by multiplexor based frequency selector. Subsequently, it has been coupled with the current-reuse voltage-controlled oscillator to reduce overall phase noise of PLL to a considerable extent. Additionally, the proposed PLL circuitry is capable of self-bandwidth switching and it is suitable for applications requiring multiple frequency bands and fast settling time. Circuit implementation of this PLL performed at 130 nm-CMOS technology-node resulted in the design area of 0.037 mm2, power consumption of 360µW at 0.9 GHz and a settling time of 22 µS. In comparison with the state-of-the-art implementations, our design occupies 98% smaller area and consumes 50% lesser power.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129327077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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