International Journal of Parallel Programming最新文献

{"title":"Meerkat: A Framework for Dynamic Graph Algorithms on GPUs","authors":"Kevin Jude Concessao, Unnikrishnan Cheramangalath, Ricky Dev, Rupesh Nasre","doi":"10.1007/s10766-024-00774-z","DOIUrl":"https://doi.org/10.1007/s10766-024-00774-z","url":null,"abstract":"<p>Graph algorithms are challenging to implement due to their varying topology and irregular access patterns. Real-world graphs are dynamic in nature and routinely undergo edge and vertex additions, as well as, deletions. Typical examples of dynamic graphs are social networks, collaboration networks, and road networks. Applying static algorithms repeatedly on dynamic graphs is inefficient. Further, due to the rapid growth of unstructured and semi-structured data, graph algorithms demand efficient parallel processing. Unfortunately, we know only a little about how to efficiently process dynamic graphs on massively parallel architectures such as GPUs. Existing approaches to represent and process dynamic graphs are either not general or are inefficient. In this work, we propose a graph library for dynamic graph algorithms over a GPU-tailored graph representation and exploits the <i>warp-cooperative work-sharing execution model</i>. The library, named <span>Meerkat</span>, builds upon a recently proposed dynamic graph representation on GPUs. This representation exploits a hashtable-based mechanism to store a vertex’s neighborhood. <span>Meerkat</span> also enables fast iteration through a group of vertices, a pattern common and crucial for achieving performance in graph applications. Our framework supports dynamic edge additions and edge deletions, along with their batched versions. Based on the efficient iterative patterns encoded in <span>Meerkat</span>, we implement dynamic versions of popular graph algorithms such as breadth-first search, single-source shortest paths, triangle counting, PageRank, and weakly connected components. We evaluated our implementations over the ones in other publicly available dynamic graph data structures and frameworks: <i>GPMA</i>, <i>Hornet</i>, and <i>faimGraph</i>. Using a variety of real-world graphs, we observe that <span>Meerkat</span> significantly improves the efficiency of the underlying dynamic graph algorithm, outperforming these frameworks.</p>","PeriodicalId":14313,"journal":{"name":"International Journal of Parallel Programming","volume":"16 1","pages":""},"PeriodicalIF":1.5,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142256750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Intelligent Page Migration on Heterogeneous Memory by Using Transformer","authors":"Songwen Pei, Wei Qin, Jianan Li, Junhao Tan, Jie Tang, Jean-Luc Gaudiot","doi":"10.1007/s10766-024-00776-x","DOIUrl":"https://doi.org/10.1007/s10766-024-00776-x","url":null,"abstract":"<p>Locality-based migration strategies are widely used in existing memory space management. Such type of strategies are consistently confronts with challenges in efficiently managing pages migration within constrained memory space, especially when new architecture such as hybrid of DRAM and NVM are emerging. Here we propose TransMigrator, an innovative predictive page migration model based on transformer architecture, which obtains a qualitative leap in the breadth and accuracy of prediction compared with traditional local-based methods. TransMigrator utilizes an end-to-end neural network to learn memory access behavior and page migration record in the long-term history and predict the most likely next page to fetch. Furthermore, a migration-management mechanism is designed to support the page-feeding from predictor, which in another way enhance the model robustness. The model achieves an average prediction accuracy better than 0.72, and saves an average of 0.24 access time overhead compared to strategies such as AC-CLOCK, THMigrator, and VC-HMM.</p>","PeriodicalId":14313,"journal":{"name":"International Journal of Parallel Programming","volume":"19 1","pages":""},"PeriodicalIF":1.5,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142183337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and Performance Evaluation of a Novel High-Speed Hardware Architecture for Keccak Crypto Coprocessor","authors":"Mustafa Sanlı","doi":"10.1007/s10766-024-00777-w","DOIUrl":"https://doi.org/10.1007/s10766-024-00777-w","url":null,"abstract":"<p>The Keccak algorithm plays a significant role in ensuring the security and confidentiality of data in modern information systems. However, it involves computational complexities that can hinder high-performance applications. This paper proposes a novel high-performance hardware architecture for the Keccak algorithm to address this problem. Our proposed hardware architecture exploits existing parallelisms in the Keccak algorithm to optimize its execution in terms of both speed and resource efficiency. By thoroughly analyzing the Keccak algorithm's structure and building blocks, we adapted our hardware architecture to take full advantage of the capabilities of modern FPGAs and ASICs. Key features of the high-performance hardware architecture include parallelized computation blocks, efficient digital design and a streamlined data path. In addition to these, we also make use of hardware level design considerations such as FPGA floorplanning, pipelining and bit-level parallelisms to increase the performance of our design. All these design considerations contribute to significantly increased processing speeds surpassing traditional software-based approaches and previous hardware-based implementations. Our design also minimizes resource usage, making it applicable to a wide variety of embedded and cryptographic systems. This makes our design suitable for applications that require both high throughput and secure data processing.</p>","PeriodicalId":14313,"journal":{"name":"International Journal of Parallel Programming","volume":"24 1","pages":""},"PeriodicalIF":1.5,"publicationDate":"2024-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142183338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"RMOWOA: A Revamped Multi-Objective Whale Optimization Algorithm for Maximizing the Lifetime of a Network in Wireless Sensor Networks","authors":"Bhanu Dwivedi, Bachu Dushmanta Kumar Patro","doi":"10.1007/s10766-024-00775-y","DOIUrl":"https://doi.org/10.1007/s10766-024-00775-y","url":null,"abstract":"<p>Wireless sensor networks (WSNs) consist of sensor nodes that detect, process, and transmit various types of information to a base station unit. The development of energy-efficient routing protocols is a crucial challenge in WSNs. This study proposes a novel algorithm called RMOWOA, i.e., <i>Revamped Multi-Objective Whale Optimization Algorithm</i>, which utilizes concentric circles with different radii to partition the network. The circles are divided into eight equal sectors, and sections are formed at the intersections of sectors and layers. Each section contains a small number of nodes, and an agent is selected based on specific criteria. The nodes within each section transmit their detected information to the corresponding agent or cluster head. This process is repeated until the base station receives the data. The selection of agents is based on a WOA-based approach, known for enhancing the network's lifetime. The selected agent aggregates the data, performs redundant residue number-based error detection and rectification, and forwards the information to the lower segment's agent within that sector. The proposed RMOWOA algorithm is evaluated through simulation analysis and compared with established benchmark cluster head selection schemes such as SFA- Cluster Head Selection, FCGWO-Cluster Head Selection, and ABC-Cluster Head Selection. The experimental results of the RMOWOA algorithm demonstrate reduced energy consumption and extended network lifespan by effectively balancing the ratio of alive and dead nodes in WSNs.</p>","PeriodicalId":14313,"journal":{"name":"International Journal of Parallel Programming","volume":"23 1","pages":""},"PeriodicalIF":1.5,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141933442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimizing Three-Dimensional Stencil-Operations on Heterogeneous Computing Environments","authors":"Nina Herrmann, Justus Dieckmann, Herbert Kuchen","doi":"10.1007/s10766-024-00769-w","DOIUrl":"https://doi.org/10.1007/s10766-024-00769-w","url":null,"abstract":"<p>Complex algorithms and enormous data sets require parallel execution of programs to attain results in a reasonable amount of time. Both aspects are combined in the domain of three-dimensional stencil operations, for example, computational fluid dynamics. This work contributes to the research on high-level parallel programming by discussing the generalizable implementation of a three-dimensional stencil skeleton that works in heterogeneous computing environments. Two exemplary programs, a gas simulation with the Lattice Boltzmann method, and a mean blur, are executed in a multi-node multi-graphics processing units environment, proving the runtime improvements in heterogeneous computing environments compared to a sequential program.</p>","PeriodicalId":14313,"journal":{"name":"International Journal of Parallel Programming","volume":"24 1","pages":""},"PeriodicalIF":1.5,"publicationDate":"2024-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141506740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Orchestration Extensions for Interference- and Heterogeneity-Aware Placement for Data-Analytics","authors":"Achilleas Tzenetopoulos, Dimosthenis Masouros, Sotirios Xydis, Dimitrios Soudris","doi":"10.1007/s10766-024-00771-2","DOIUrl":"https://doi.org/10.1007/s10766-024-00771-2","url":null,"abstract":"<p>Today, there is an ever-increasing number of workloads pushed and executed on the Cloud. Data center operators and Cloud providers have embraced application co-location and multi-tenancy as first-class system design concerns to effectively serve and manage these huge computational demands. In addition, the continuous advancements in the computers’ hardware technology have made it possible to seamlessly leverage heterogeneous pools of physical machines in data center environments. Even though current modern Cloud schedulers and orchestrators adopt application-aware policies to achieve automation of time-consuming management tasks at scale, e.g., resource provisioning, they still rely on coarse-grained system metrics, such as CPU and/or memory utilization to place incoming applications, thus, not considering (1) interference effects that are provoked by co-located tasks, and (2) the impact on performance caused by the diversity of heterogeneous systems’ characteristics. The lack of such knowledge in existing state-of-the-art orchestration solutions results in their inability to perform efficient allocations, which negatively impacts the overall latency distribution delivered by the infrastructure. In this paper, to alleviate this inefficiency, we present a machine learning (ML) based Cloud orchestration extension that takes into account both resource interference and heterogeneity. The framework adequately schedules data-analytics applications on a pool of heterogeneous resources. We evaluate our proposed solution on different application mixes and co-location scenarios. We show that the proposed framework improves the tail latency of the distribution of the deployed applications by up to 3.6x compared to the state-of-the-art Kubernetes scheduler.</p>","PeriodicalId":14313,"journal":{"name":"International Journal of Parallel Programming","volume":"65 1","pages":""},"PeriodicalIF":1.5,"publicationDate":"2024-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141169831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-Level Programming of FPGA-Accelerated Systems with Parallel Patterns","authors":"Björn Birath, August Ernstsson, John Tinnerholm, Christoph Kessler","doi":"10.1007/s10766-024-00770-3","DOIUrl":"https://doi.org/10.1007/s10766-024-00770-3","url":null,"abstract":"<p>As a result of frequency and power limitations, multi-core processors and accelerators are becoming more and more prevalent in today’s systems. To fully utilize such systems, heterogeneous parallel programming is needed, but this introduces new complexities to the development. High-level frameworks such as SkePU have been introduced to help alleviate these complexities. SkePU is a skeleton programming framework based on a set of programming constructs implementing computational parallel patterns, while presenting a sequential interface to the programmer. Using the various skeleton backends, SkePU programs can execute, without source code modification, on multiple types of hardware such as CPUs, GPUs, and clusters. This paper presents the design and implementation of a new backend for SkePU, adding support for FPGAs. We also evaluate the effect of FPGA-specific optimizations in the new backend and compare it with the existing GPU backend, where the actual devices used are of similar vintage and price point. For simple examples, we find that the FPGA-backend’s performance is similar to that of the existing backend for GPUs, while it falls behind in more complex tasks. Finally, some shortcomings in the backend are highlighted and discussed, along with potential solutions.</p>","PeriodicalId":14313,"journal":{"name":"International Journal of Parallel Programming","volume":"52 1","pages":""},"PeriodicalIF":1.5,"publicationDate":"2024-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141169753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"GraphTango: A Hybrid Representation Format for Efficient Streaming Graph Updates and Analysis","authors":"Alif Ahmed, Farzana Ahmed Siddique, Kevin Skadron","doi":"10.1007/s10766-024-00768-x","DOIUrl":"https://doi.org/10.1007/s10766-024-00768-x","url":null,"abstract":"<p>Streaming graph processing performs batched updates and analytics on a time-evolving graph. The underlying representation format of the graph largely determines the throughputs of these updates and analytics phases. Existing representation formats usually employ variations of hash tables or adjacency lists. However, a recent study showed that the adjacency-list-based approaches perform poorly on heavy-tailed graphs, and the hash table-based approaches suffer on short-tailed graphs. We propose GraphTango, a hybrid representation format that provides excellent update and analytics throughput regardless of the graph’s degree distribution. GraphTango dynamically switches among three different formats based on a vertex’s degree: (i) Low-degree vertices store the edges directly with the neighborhood metadata, confining accesses to a single cache line, (2) Medium-degree vertices use adjacency lists, and (3) High-degree vertices use hash tables as well as adjacency lists. In this case, the adjacency list provides fast traversal during the analytics phase, while the hash table provides constant-time lookups during the update phase. We further optimized the performance by designing an open-addressing-based hash table that fully utilizes every fetched cache line. In addition, we developed a thread-local lock-free memory pool that allows fast growing/shrinking of the adjacency lists and hash tables in a multi-threaded environment. We evaluated GraphTango with the help of the SAGA-Bench framework and compared it with four other representation formats: Stinger, Degree-aware Robin Hood Hashing, and two adjacency list-based formats with different workload balancing scheme. On average, GraphTango provides 4.5x higher insertion throughput, 3.2x higher deletion throughput, and 1.1x higher analytics throughput over the <i>next best</i> format. Furthermore, we integrated GraphTango with the state-of-the-art graph processing frameworks DZiG and RisGraph. Compared to the <i>vanilla DZiG</i> and <i>vanilla RisGraph</i>, [<i>GraphTango + DZiG</i>] and [<i>GraphTango + RisGraph</i>] reduces the average batch processing time by 2.3x and 1.5x, respectively.</p>","PeriodicalId":14313,"journal":{"name":"International Journal of Parallel Programming","volume":"20 1","pages":""},"PeriodicalIF":1.5,"publicationDate":"2024-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141061362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Yet Another Lock-Free Atom Table Design for Scalable Symbol Management in Prolog","authors":"","doi":"10.1007/s10766-024-00766-z","DOIUrl":"https://doi.org/10.1007/s10766-024-00766-z","url":null,"abstract":"<h3>Abstract</h3> <p>Prolog systems rely on an atom table for symbol management, which is usually implemented as a dynamically resizeable hash table. This is ideal for single threaded execution, but can become a bottleneck in a multi-threaded scenario. In this work, we replace the original atom table implementation in the YAP Prolog system with a lock-free hash-based data structure, named Lock-free Hash Tries (LFHT), in order to provide efficient and scalable symbol management. Being lock-free, the new implementation also provides better guarantees, namely, immunity to priority inversion, to deadlocks and to livelocks. Performance results show that the new lock-free LFHT implementation has better results in single threaded execution and much better scalability than the original lock based dynamically resizing hash table.</p>","PeriodicalId":14313,"journal":{"name":"International Journal of Parallel Programming","volume":"161 1","pages":""},"PeriodicalIF":1.5,"publicationDate":"2024-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140201434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Automatic Discovery of Collective Communication Patterns in Parallelized Task Graphs","authors":"Fabian Knorr, Philip Salzmann, Peter Thoman, Thomas Fahringer","doi":"10.1007/s10766-024-00767-y","DOIUrl":"https://doi.org/10.1007/s10766-024-00767-y","url":null,"abstract":"<p>Collective communication APIs equip MPI vendors with the necessary context to optimize cluster-wide operations on the basis of theoretical complexity models and characteristics of the involved interconnects. Modern HPC runtime systems with a programmability focus can perform dependency analysis to eliminate the need for manual communication entirely. Profiting from optimized collective routines in this context often requires global analysis of the implicit point-to-point communication pattern or tight constrains on the data access patterns allowed inside kernels. The Celerity API provides a high degree of freedom for both runtime implementors and application developers by tieing transparent work assignment to data access patterns through user-defined range-mapper functions. Canonically, data dependencies are resolved through an intra-node coherence model and inter-node point-to-point communication. This paper presents Collective Pattern Discovery (CPD), a fully distributed, coordination-free method for detecting collective communication patterns on parallelized task graphs. Through extensive scheduling and communication microbenchmarks as well as a strong scaling experiment on a compute-intensive application, we demonstrate that CPD can achieve substantial performance gains in the Celerity model.</p>","PeriodicalId":14313,"journal":{"name":"International Journal of Parallel Programming","volume":"18 1","pages":""},"PeriodicalIF":1.5,"publicationDate":"2024-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140201435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}