Design and Performance Evaluation of a Novel High-Speed Hardware Architecture for Keccak Crypto Coprocessor

Abstract

The Keccak algorithm plays a significant role in ensuring the security and confidentiality of data in modern information systems. However, it involves computational complexities that can hinder high-performance applications. This paper proposes a novel high-performance hardware architecture for the Keccak algorithm to address this problem. Our proposed hardware architecture exploits existing parallelisms in the Keccak algorithm to optimize its execution in terms of both speed and resource efficiency. By thoroughly analyzing the Keccak algorithm's structure and building blocks, we adapted our hardware architecture to take full advantage of the capabilities of modern FPGAs and ASICs. Key features of the high-performance hardware architecture include parallelized computation blocks, efficient digital design and a streamlined data path. In addition to these, we also make use of hardware level design considerations such as FPGA floorplanning, pipelining and bit-level parallelisms to increase the performance of our design. All these design considerations contribute to significantly increased processing speeds surpassing traditional software-based approaches and previous hardware-based implementations. Our design also minimizes resource usage, making it applicable to a wide variety of embedded and cryptographic systems. This makes our design suitable for applications that require both high throughput and secure data processing.