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Proceedings of the 2016 International Symposium on Low Power Electronics and Design最新文献

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Design and implementation of nonvolatile power-gating SRAM using SOTB technology 基于SOTB技术的非易失性功率门控SRAM的设计与实现
Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934628
Y. Shuto, Shuu'ichirou Yamamoto, S. Sugahara
{"title":"Design and implementation of nonvolatile power-gating SRAM using SOTB technology","authors":"Y. Shuto, Shuu'ichirou Yamamoto, S. Sugahara","doi":"10.1145/2934583.2934628","DOIUrl":"https://doi.org/10.1145/2934583.2934628","url":null,"abstract":"Power-gating (PG) architectures employing nonvolatile state/data retention, called nonvolatile PG (NVPG), are expected as a highly efficient energy reduction technique for high-performance microprocessors and mobile/wearable SoC devices. In this paper, NVPG architecture for SRAM is demonstrated. A 1kb nonvolatile SRAM (NV-SRAM) array with the peripheral circuits is implemented using 65nm silicon-on-thin-buried-oxide (SOTB) technology. The cell design and array architectures for the NV-SRAM are discussed from the viewpoints of the stability and energy efficiency. Energy performance of the NVPG architecture for NV-SRAM with various array sizes is also systematically analyzed using a performance index of break-even time (BET). The array structure and its peripherals strongly affect BET. The body-bias-induced leakage reduction for the peripherals is highly effective at reducing BET. The NVPG architecture with NV-SRAM would be adaptable to core-level power-gating of multi-/many-core processors and SoC devices, and it could also be promising as a solution for the dark silicon problem.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134022991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Programmable Analog-to-Information Converter for Agile Biosensing 用于敏捷生物传感的可编程模拟-信息转换器
Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934596
Aosen Wang, Zhanpeng Jin, Wenyao Xu
{"title":"A Programmable Analog-to-Information Converter for Agile Biosensing","authors":"Aosen Wang, Zhanpeng Jin, Wenyao Xu","doi":"10.1145/2934583.2934596","DOIUrl":"https://doi.org/10.1145/2934583.2934596","url":null,"abstract":"In recent years, the analog-to-information converter (AIC), based on compressed sensing (CS) paradigm, is a promising solution to overcome the performance and energy-efficiency limitations of traditional analog-to-digital converters (ADC). Especially, AIC can enable sub-Nyquist signal sampling proportional to the intrinsic information in biomedical applications. However, the legacy AIC structure is tailored toward specific applications, which lacks of flexibility and prevents its universality. In this paper, we introduce a novel programmable AIC architecture, Pro-AIC, to enable effective configurability and reduce its energy overhead by integrating efficient multiplexing hardware design. To improve the quality and time-efficiency of Pro-AIC configuration, we also develop a rapid configuration algorithm, called RapSpiral, to quickly find the near-optimal parameter configuration in Pro-AIC architecture. Specifically, we present a design metric, trade-off penalty, to quantitatively evaluate the performance-energy trade-off. The RapSpiral controls a penalty-driven shrinking triangle to progressively approximate to the optimal trade-off. Our proposed RapSpiral is with log(n) complexity yet high accuracy, without pretraining and complex parameter tuning procedure. RapSpiral is also probable to avoid the local minimum pitfalls. Experimental results indicate that our RapSpiral algorithm can achieve more than 30x speedup compared with the brute force algorithm, with only about 3% trade-off compromise to the optimum in Pro-AIC. Furthermore, the scalability is also verified on larger size benchmarks.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128313843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Energy-Aware Approach to Noise-Robust Moving Object Detection for Low-Power Wireless Image Sensor Platforms 基于能量感知的低功耗无线图像传感器平台抗噪运动目标检测方法
Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934618
J. Ko, S. Mukhopadhyay
{"title":"An Energy-Aware Approach to Noise-Robust Moving Object Detection for Low-Power Wireless Image Sensor Platforms","authors":"J. Ko, S. Mukhopadhyay","doi":"10.1145/2934583.2934618","DOIUrl":"https://doi.org/10.1145/2934583.2934618","url":null,"abstract":"This paper presents an energy-aware approach to moving object detection that requires very low computation and memory while ensuring robust performance under noisy environments. The proposed approach is integrated into a wireless image sensor platform with a block-based processing unit and the motion JPEG encoder. The sensor platform is designed as an ASIC in 130nm CMOS for energy/area analysis, as well as prototyped into Virtex-5 FPGA for functional validation. The sensor platform designed with the proposed approach consumes less energy and area than the platforms with the existing methods such as Gaussian Mixture Model, while maintaining a reliable delivery of region-of-interest.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130027712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJ 具有创新200nm纳米环形MTJ的4Kb STT-MRAM的设计与实现
Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934611
Zheng Li, Xiuyuan Bi, Hai Helen Li, Yiran Chen, J. Qin, Peng Guo, W. Kong, W. Zhan, Xiufeng Han, Hong Zhang, Lingling Wang, Guanping Wu, Hanming Wu
{"title":"Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJ","authors":"Zheng Li, Xiuyuan Bi, Hai Helen Li, Yiran Chen, J. Qin, Peng Guo, W. Kong, W. Zhan, Xiufeng Han, Hong Zhang, Lingling Wang, Guanping Wu, Hanming Wu","doi":"10.1145/2934583.2934611","DOIUrl":"https://doi.org/10.1145/2934583.2934611","url":null,"abstract":"Programmability is as a severe challenge in development of spin-transfer torque magnetic random access memory (STT-MRAM). Theoretical analysis have indicated that nano-ring shaped magnetic tunneling junction (NR-MTJ) can achieve lower write current and higher write reliability compared to conventional elliptical-shaped MTJ (E-MTJ). In this work, we successfully patterned the NR-MTJ with 200nm outer diameter and 120nm inner diameter in commercial manufacturing facility, designed and fabricated a 4Kb STT-MRAM test chip with NR-MTJs. Testing results demonstrated successful read and write functionalities of our chip, and proved the theocratically-predicted electrical properties of NR-MTJs.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134634780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Data-Driven Low-Cost On-Chip Memory with Adaptive Power-Quality Trade-off for Mobile Video Streaming 基于自适应电能质量权衡的数据驱动低成本片上存储器
Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934619
Dongliang Chen, J. Edstrom, Xiaowei Chen, W. Jin, Jinhui Wang, Na Gong
{"title":"Data-Driven Low-Cost On-Chip Memory with Adaptive Power-Quality Trade-off for Mobile Video Streaming","authors":"Dongliang Chen, J. Edstrom, Xiaowei Chen, W. Jin, Jinhui Wang, Na Gong","doi":"10.1145/2934583.2934619","DOIUrl":"https://doi.org/10.1145/2934583.2934619","url":null,"abstract":"Nowadays, people enjoy watching mobile videos more than ever and mobile video streaming contributes to the majority of the total mobile data traffic. However, due to the high power consumption of mobile video decoders, especially the on-chip memories, short battery life represents one of the biggest contributors to user dissatisfaction. Various mobile embedded memory techniques have been investigated to reduce power consumption and prolong battery life. Unfortunately, the existing hardware-level research suffers from high implementation complexity and large overhead. In this paper, by introducing advanced data-mining techniques, we investigate meaningful data patterns hidden in mobile video data and apply the identified patterns to implement a low-power flexible hardware design with dynamic power-quality trade-off. A 45nm 32kb SRAM is presented that enables three levels of power-quality trade-off (up to 43.7% power savings) with negligible area overhead (0.06%).","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114537389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Session details: Heterogeneous Computing in Data Centers for Energy Efficiency 会议详细内容:能源效率数据中心的异构计算
Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/3256018
J. Cong
{"title":"Session details: Heterogeneous Computing in Data Centers for Energy Efficiency","authors":"J. Cong","doi":"10.1145/3256018","DOIUrl":"https://doi.org/10.1145/3256018","url":null,"abstract":"","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115473057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency 基于域壁存储器的位宽可扩展性和高能效卷积神经网络
Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934602
Jinil Chung, Jongsun Park, Swaroop Ghosh
{"title":"Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency","authors":"Jinil Chung, Jongsun Park, Swaroop Ghosh","doi":"10.1145/2934583.2934602","DOIUrl":"https://doi.org/10.1145/2934583.2934602","url":null,"abstract":"In the hardware implementation of deep learning algorithms such as Convolutional Neural Networks (CNNs), vector-vector multiplications and memories for storing parameters take a significant portion of area and power consumption. In this paper, we propose a Domain Wall Memory (DWM) based design of CNN convolutional layer. In the proposed design, the resistive cell sensing mechanism is efficiently exploited to design a low-cost DWM-based cell arrays for storing parameters. The unique serial access mechanism and small footprint of DWM are also used to reduce the area and power cost of the input registers for aligning inputs. Contrary to the conventional implementation using Memristor-Based Crossbar (MBC), the bit-width of the proposed CNN convolutional layer is extendable for high resolution classifications and training. Simulation results using 65 nm CMOS process show that the proposed design archives 34% of energy savings compared to the conventional MBC based design approach.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117064284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Innovation for Future Connected Compute 未来互联计算的创新
Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2962721
V. Ilderem
{"title":"Innovation for Future Connected Compute","authors":"V. Ilderem","doi":"10.1145/2934583.2962721","DOIUrl":"https://doi.org/10.1145/2934583.2962721","url":null,"abstract":"Internet of Things (IOT) is a rapidly growing market that is being targeted by many companies world-wide to address significant local or global challenges. The projections for growth in this area are for up to 50 billion devices connected to the internet by 2020. Further trends in this market point to an exciting opportunity to truly pursue pervasive computing where energy efficient connected devices is one of, if not the most important, technology needed.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130210245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Energy-Efficient Computational Model for Uncertainty Management in Dynamically Changing Networked Wearables 动态变化网络可穿戴设备不确定性管理的节能计算模型
Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934617
Ramyar Saeedi, Ramin Fallahzadeh, Parastoo Alinia, Hassan Ghasemzadeh
{"title":"An Energy-Efficient Computational Model for Uncertainty Management in Dynamically Changing Networked Wearables","authors":"Ramyar Saeedi, Ramin Fallahzadeh, Parastoo Alinia, Hassan Ghasemzadeh","doi":"10.1145/2934583.2934617","DOIUrl":"https://doi.org/10.1145/2934583.2934617","url":null,"abstract":"The utility of wearables is currently limited to lab experiments and controlled environments mainly because computational algorithms embedded in wearables fail to produce accurate measurements in uncontrolled, dynamically changing, and potentially harsh environments. With the exponentially growing adoption of these systems in human-centered Internet-of-Things (IoT) applications, development of resource-efficient solutions to enhance the accuracy of this systems remains a considerable research challenge. In this paper, we introduce an energy-efficient framework for uncertainty management of networked wearables. The core components of our framework are anomaly screening units for detecting anomalies that require handling, thus resulting in one order of magnitude less energy consumption compared to the conventional frameworks. Furthermore, our screening approach achieves 98.3% accuracy in detecting anomalies based on real data collected with wearable motion sensors.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132147165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Session details: Hardware Security 会话详细信息:硬件安全
Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/3256017
J. Gu, Carlos Tokunaga
{"title":"Session details: Hardware Security","authors":"J. Gu, Carlos Tokunaga","doi":"10.1145/3256017","DOIUrl":"https://doi.org/10.1145/3256017","url":null,"abstract":"","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125406692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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