Design and implementation of nonvolatile power-gating SRAM using SOTB technology

Power-gating (PG) architectures employing nonvolatile state/data retention, called nonvolatile PG (NVPG), are expected as a highly efficient energy reduction technique for high-performance microprocessors and mobile/wearable SoC devices. In this paper, NVPG architecture for SRAM is demonstrated. A 1kb nonvolatile SRAM (NV-SRAM) array with the peripheral circuits is implemented using 65nm silicon-on-thin-buried-oxide (SOTB) technology. The cell design and array architectures for the NV-SRAM are discussed from the viewpoints of the stability and energy efficiency. Energy performance of the NVPG architecture for NV-SRAM with various array sizes is also systematically analyzed using a performance index of break-even time (BET). The array structure and its peripherals strongly affect BET. The body-bias-induced leakage reduction for the peripherals is highly effective at reducing BET. The NVPG architecture with NV-SRAM would be adaptable to core-level power-gating of multi-/many-core processors and SoC devices, and it could also be promising as a solution for the dark silicon problem.