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Design of a Dual-Mode NoC Router Integrated with Network Interface for AMBA-based IPs 基于amba的双模NoC路由器集成网络接口的设计
2006 IEEE Asian Solid-State Circuits Conference Pub Date : 2006-12-01 DOI: 10.1109/ASSCC.2006.357888
Shih-Hsun Hsu, Yu-Xuan Lin, J. Jou
{"title":"Design of a Dual-Mode NoC Router Integrated with Network Interface for AMBA-based IPs","authors":"Shih-Hsun Hsu, Yu-Xuan Lin, J. Jou","doi":"10.1109/ASSCC.2006.357888","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357888","url":null,"abstract":"Networks-on-a-chip (NoC) is a new architectural template, which helps to meet many of challenges of designing a complex system-on-a-chip (SoC). In the paper, we introduce the on-chip network of and propose the dual-mode router for NoC which provides both guaranteed and best-effort communication services. We adopt the recording table for circuit switching to support the guaranteed service, and in order to sufficiently utilize the bandwidth of the network we add the wormhole switching which contains several virtual channels. Additionally, our router integrates the standard interface with AMBA AHB for easier integration of the intellectual properties (IPs) of NoC. The benchmark router with 5 32-bit ports can operate at 100 MHz and the bandwidth per link of the router can be up to 3.2 Gbps. The performance of the router is enough for providing an HDTV application on NoC.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124987700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A Digitally Calibrated Current-Voltage Feedback Transconductor in 0.13-μm CMOS Process 基于0.13 μm CMOS工艺的数字校准电流-电压反馈晶体管
2006 IEEE Asian Solid-State Circuits Conference Pub Date : 2006-12-01 DOI: 10.1109/ASSCC.2006.357875
Ying-Zu Lin, Yen-Ting Liu, Soon-Jyh Chang
{"title":"A Digitally Calibrated Current-Voltage Feedback Transconductor in 0.13-μm CMOS Process","authors":"Ying-Zu Lin, Yen-Ting Liu, Soon-Jyh Chang","doi":"10.1109/ASSCC.2006.357875","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357875","url":null,"abstract":"A digitally calibrated transconductor for high-speed operation with its linearity enhanced by negative feedback is proposed. This voltage-to-current converter is mainly composed of two parts: an operational transconductance amplifier (OTA) and a pair of feedback resistors. The measured spurious free dynamic range (SFDR) of the transconductor is 72.6 dB when the input frequency is 100 MHz. To compensate common-mode deviation due to process variation, digital calibration circuits are added. Fabricated in TSMC 0.13-μm CMOS process, the transconductor occupies 250 × 200 μm2 active area and consumes 5.06 mW from a 1.2-V supply.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117318515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 2.5 14-bit 180-mW Cascaded ΣΔ ADC for ADSL2+ Applications 用于ADSL2+应用的2.5 14位180 mw级联ΣΔ ADC
2006 IEEE Asian Solid-State Circuits Conference Pub Date : 2006-12-01 DOI: 10.1109/ASSCC.2006.357851
Teng-Hung Chang, Lan-Rong Dung, Jwin-Yen Guo, Kai-Jiun Yang
{"title":"A 2.5 14-bit 180-mW Cascaded ΣΔ ADC for ADSL2+ Applications","authors":"Teng-Hung Chang, Lan-Rong Dung, Jwin-Yen Guo, Kai-Jiun Yang","doi":"10.1109/ASSCC.2006.357851","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357851","url":null,"abstract":"This paper presents a sigma-delta (ΣΔ) analog-to-digital converter (ADC) for the extended bandwidth asymmetric digital subscriber line application (ADSL2+). The core of the ADC is a cascaded 2-1-1 ΣΔ modulator that employs a resonator-based topology in the first stage, three tri-level quantizers, and two different pairs of reference voltages. As shown in the experimental result, for a 2.2 MHz signal bandwidth, the ADC achieves a dynamic range of 86 dB and a peak signal-to-noise and distortion ratio (SNDR) of 78 dB with an oversampling ratio of 16. It is implemented in a 0.25-μm CMOS technology, in a 2.4-mm2 active area including decimation filter and reference voltage buffers, and dissipates 180 mW from a 2.5-V power supply.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134609975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 0.6-V, 6.8-μW Embedded SRAM for Ultra-low Power SoC 用于超低功耗SoC的0.6 v, 6.8 μ w嵌入式SRAM
2006 IEEE Asian Solid-State Circuits Conference Pub Date : 2006-11-13 DOI: 10.1109/ASSCC.2006.357914
Kyomin Sohn, Sungdae Choi, Jeong-Ho Woo, Joo-Young Kim, H. Yoo
{"title":"A 0.6-V, 6.8-μW Embedded SRAM for Ultra-low Power SoC","authors":"Kyomin Sohn, Sungdae Choi, Jeong-Ho Woo, Joo-Young Kim, H. Yoo","doi":"10.1109/ASSCC.2006.357914","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357914","url":null,"abstract":"A novel embedded SRAM is proposed with features of high reliability and low power consumption. The critical control signals are made in correspondence to clock-duty cycle for high reliability. A hybrid precharge scheme is adopted for low power consumption. Additionally, an asymmetric read-write scheme is useful in a slow-but-steady write situation such as a control SoC for BSN (body sensor network). The fabricated 128-kb embedded SRAM consumes 117-μW at the worst case and 6.8-μW at normal write operation in a 0.6-V supply voltage.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131758057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low Power 16-bit RISC with Lossless Compression Accelerator for Body Sensor Network System 具有无损压缩加速器的低功耗16位RISC人体传感器网络系统
2006 IEEE Asian Solid-State Circuits Conference Pub Date : 2006-11-13 DOI: 10.1109/ASSCC.2006.357887
Hyejung Kim, Sungdae Choi, H. Yoo
{"title":"A Low Power 16-bit RISC with Lossless Compression Accelerator for Body Sensor Network System","authors":"Hyejung Kim, Sungdae Choi, H. Yoo","doi":"10.1109/ASSCC.2006.357887","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357887","url":null,"abstract":"A low power 16-bit RISC is proposed for body sensor network system. The proposed IPEEP scheme provides zero overhead for the wakeup operation. The lossless compression accelerator is embedded in the RISC to support the low energy data compression. The accelerator consists of 16times16-bit storage array which has vertical and horizontal access path. By using the accelerator the energy consumption of the lossless compression operation is reduced by 93.8%. The RISC is implemented by 1-poly 6-metal 0.18 um CMOS technology with 16 k gates. It operates at 4 MHz and consumes 24.2 uW at 0.6 V supply voltage.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133513499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A TCAM-based Periodic Event Generator for Multi-Node Management in the Body Sensor Network 基于tcam的人体传感器网络多节点管理周期事件发生器
2006 IEEE Asian Solid-State Circuits Conference Pub Date : 2006-11-13 DOI: 10.1109/ASSCC.2006.357912
Sungdae Choi, Kyomin Sohn, Joo-Young Kim, Jerald Yoo, H. Yoo
{"title":"A TCAM-based Periodic Event Generator for Multi-Node Management in the Body Sensor Network","authors":"Sungdae Choi, Kyomin Sohn, Joo-Young Kim, Jerald Yoo, H. Yoo","doi":"10.1109/ASSCC.2006.357912","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357912","url":null,"abstract":"Low-power periodic event generation is essential for a node controller in the network system with centralized control and the timer interrupt generation for various devices in a CPU. The proposed TCAM-based periodic event generator manages the issuing events with the programmed value and the number of the events is equal to the number of the word line of the TCAM block. The NAND-type TCAM cell operates with as low as 0.6 V supply voltage and the low-energy match line precharge reduces the search line transition which causes most of the search energy dissipation. The implemented event generator consumes 184-nJ energy to schedule events of 255 nodes for 24-hours, which is less than 10% of energy consumption of conventional hardware timer blocks.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124423104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 210MHz 15mW Unified Vector and Transcendental Function Unit for Handield 3-D Graphics Systems 一种用于手持式三维图形系统的210MHz 15mW统一矢量与超越函数单元
2006 IEEE Asian Solid-State Circuits Conference Pub Date : 2006-11-13 DOI: 10.1109/ASSCC.2006.357860
Byeong-Gyu Nam, Hyejung Kim, H. Yoo
{"title":"A 210MHz 15mW Unified Vector and Transcendental Function Unit for Handield 3-D Graphics Systems","authors":"Byeong-Gyu Nam, Hyejung Kim, H. Yoo","doi":"10.1109/ASSCC.2006.357860","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357860","url":null,"abstract":"A low-power, area-efficient 4-way 32-bit unified vector and transcendental function unit has been developed for programmable shaders for handheld 3-D graphics systems. It adopts the logarithmic number system (LNS) at the arithmetic core for the small-size, low-power unification and single cycle throughput with maximum 4-cycle latency of various vector and transcendental functions. A novel logarithmic conversion scheme is proposed with 0.41% of maximum conversion error. A test chip is implemented by 0.18-mum CMOS technology with 91 K gates. It operates at 210 MHz and consumes 15 mW at 1.8 V.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133647238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A CMOS Dual Class-AB Technique for Highly Linear Even Harmonic Mixer 用于高线性均匀谐波混频器的CMOS双ab类技术
2006 IEEE Asian Solid-State Circuits Conference Pub Date : 2006-11-01 DOI: 10.1109/ASSCC.2006.357927
Ming-Feng Huang, C. Kuo
{"title":"A CMOS Dual Class-AB Technique for Highly Linear Even Harmonic Mixer","authors":"Ming-Feng Huang, C. Kuo","doi":"10.1109/ASSCC.2006.357927","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357927","url":null,"abstract":"A 5.25-GHz CMOS even harmonic mixer (EHM) using a dual class-AB circuit is presented. The dual class-AB circuit in the RF stage can improve the linearity and conversion gain for wireless receivers. In addition, the dual class-AB circuit adjusting the mixing power from the frequency-doubling circuit can overcome the process variation. After an implemented chip, the measurement reveals that the proposed EHM has a power consumption of 4.13-mW, conversion gain of 13.133-dB, IIP3 of -1.033-dBm, and IIP2 of 48.267-dBm under the LO frequency of 2.623-GHz. With a measured linearity upon a high power conversion gain, the proposed EHM shows improved performance compared with other published active EHMs.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127551062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Adaptive Self Refresh Scheme for Battery Operated High-Density Mobile DRAM Applications 电池供电高密度移动DRAM应用的自适应自刷新方案
2006 IEEE Asian Solid-State Circuits Conference Pub Date : 2006-11-01 DOI: 10.1109/ASSCC.2006.357915
Jin-Hong Ahn, B. Jeong, Saeng-Hwan Kim, Shin-Ho Chu, Sung-Kwon Cho, Hanjun Lee, Min-Ho Kim, Sang-il Park, Sung-Won Shin, Jun-Ho Lee, Bong-Seok Han, Jae-Keun Hong, P. Moran, Yong Kim
{"title":"Adaptive Self Refresh Scheme for Battery Operated High-Density Mobile DRAM Applications","authors":"Jin-Hong Ahn, B. Jeong, Saeng-Hwan Kim, Shin-Ho Chu, Sung-Kwon Cho, Hanjun Lee, Min-Ho Kim, Sang-il Park, Sung-Won Shin, Jun-Ho Lee, Bong-Seok Han, Jae-Keun Hong, P. Moran, Yong Kim","doi":"10.1109/ASSCC.2006.357915","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357915","url":null,"abstract":"Self refresh current in modern DRAMs is becoming more difficult problem to handle because the decreasing cell transistor size has a negative effect on the uniformity of capacitor charge. In order to solve this issue, adaptive self refresh(ASR) scheme has been developed. A dual period based refresh is performed in the ASR scheme to reduce power dissipation using row register information. The row register information is adaptively modified according to the cell data retention characteristics. When DRAM enters self refresh mode, only the rows which were activated for write are tested using internal refresh test circuits. The test results are used to choose the appropriate period for the dual period base self refresh operation. This paper demonstrates 512M mobile SDRAM utilizing this adaptive self refresh(ASR) capability to minimize standby power to 150 uA @85degC while maintaining chip area of the conventional scheme using the same process technology.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125410883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
An 800-μW H.264 Baseline-Profile Motion Estimation Processor Core 一个800 μ w H.264基线轮廓运动估计处理器核心
2006 IEEE Asian Solid-State Circuits Conference Pub Date : 2006-11-01 DOI: 10.1109/ASSCC.2006.357861
T. Iinuma, J. Miyakoshi, Y. Murachi, T. Matsuno, M. Hamamoto, T. Ishihara, H. Kawaguchi, M. Yoshimoto, M. Miyama
{"title":"An 800-μW H.264 Baseline-Profile Motion Estimation Processor Core","authors":"T. Iinuma, J. Miyakoshi, Y. Murachi, T. Matsuno, M. Hamamoto, T. Ishihara, H. Kawaguchi, M. Yoshimoto, M. Miyama","doi":"10.1109/ASSCC.2006.357861","DOIUrl":"https://doi.org/10.1109/ASSCC.2006.357861","url":null,"abstract":"This paper describes an 800-μW H.264 baseline- profile motion estimation processor for portable video applications. It features a VLSI-oriented block partitioning strategy, a reconfigurable SIMD/systolic-array datapath architecture and a power-efficient novel SRAM circuit with a segmentation-free and horizontal/vertical accessibility. The proposed architecture can reconfigure datapath to either an SIMD or systolic array depending on processing flow. The segmentation-free access means concurrent accessibility to arbitrary consecutive pixels. The processor supports all the seven kinds of block modes, and can handle three reference frames for a VGA (640 × 480) 30-fps to QCIF (176 × 144) 15-fps sequences with a quarter-pixel accuracy. It integrates 3.3 million transistors, and occupies 2.8 × 3.1 mm2 in a 130-nm CMOS technology. The proposed processor achieves a power of 800 μW for QCIF 15-fps with one reference picture.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"226 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122611806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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