A Low Power 16-bit RISC with Lossless Compression Accelerator for Body Sensor Network System

Abstract

A low power 16-bit RISC is proposed for body sensor network system. The proposed IPEEP scheme provides zero overhead for the wakeup operation. The lossless compression accelerator is embedded in the RISC to support the low energy data compression. The accelerator consists of 16times16-bit storage array which has vertical and horizontal access path. By using the accelerator the energy consumption of the lossless compression operation is reduced by 93.8%. The RISC is implemented by 1-poly 6-metal 0.18 um CMOS technology with 16 k gates. It operates at 4 MHz and consumes 24.2 uW at 0.6 V supply voltage.