{"title":"A fully integrated Q-enhanced LC filter with 6 dB noise figure at 2.5 GHz in SOI","authors":"Xin He, W. Kuhn","doi":"10.1109/RFIC.2004.1320703","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320703","url":null,"abstract":"Q-enhanced LC filter technology offers a promising approach to remove the off-chip preselect filter still required in current transceivers. To date, previous designs fail to meet the stringent system specifications such as dynamic range and noise figure for existing wireless receivers. This paper presents an innovative prototype design targeted at Bluetooth in silicon-on-insulator (SOI) process. Drawing 5 mA from a 3 V supply, it achieves 17 dB voltage gain, approximately 6 dB noise figure, 153 dB 1-dB compression point dynamic range relative to 1 Hz bandwidth, and 70 MHz bandwidth at 2.5 GHz, suitable for industry applications.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132939783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 0.25 /spl mu/m CMOS OPLL transmitter IC for GSM and DCS","authors":"Peng-Un Su, Chun-Ming Hsu","doi":"10.1109/RFIC.2004.1320645","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320645","url":null,"abstract":"A single chip CMOS GSM/DCS dual-band offset-PLL transmitter is presented in this paper. This chip includes a quadrature modulator and an offset-PLL (OPLL) modulation loop. Except for the loop filter and the high-power voltage controlled oscillator (TX VCO), everything is integrated into this chip to form a dual-band transmitter. This transmitter IC is fabricated in 0.25 /spl mu/m CMOS process. The current consumption without TX VCO is about 23 mA under 2.7 V power supply for both bands. The measured rms and peak phase errors for GMSK modulated signals are about 1/spl deg/ and 2.4/spl deg/, respectively. The measurements show comparable performance to its BiCMOS counterparts.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116277059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"V-band and W-band SiGe bipolar low-noise amplifiers and voltage-controlled oscillators","authors":"B. Floyd","doi":"10.1109/RFIC.2004.1320601","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320601","url":null,"abstract":"LNAs and VCOs operating between 50 and 86 GHz have been implemented using a 0.12-/spl mu/m, 200-GHz SiGe bipolar technology. Unbalanced LNAs at 50, 60, and 77 GHz show /spl sim/15 dB of gain, drawing 2, 6, and 8 mA from 1.8 V, respectively. The iCP/sub 1dB/ for the LNAs are from -17 to -20 dBm. The noise figure of the 60-GHz LNA is 4.5 dB. Balanced amplifiers composed of two parallel LNAs with branch-line couplers at the input, and output have also been demonstrated at 60 and 77 GHz, showing 14 and 12-dB gain, respectively. Differential Colpitts VCOs have been implemented at 53, 67, and 85 GHz. Phase noises at a 1-MHz offset are -100, -98, and -94 dBc/Hz, respectively, while tuning ranges are 3.7%, 3.1%, and 2.7%. Each VCO consumes roughly 25 mW, and provides -8 dBm output power to 100 /spl Omega/ differential.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115079075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Wireless, remotely powered telemetry in 0.25 /spl mu/m CMOS","authors":"F. Koçer, P. Walsh, M. Flynn","doi":"10.1109/RFIC.2004.1320615","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320615","url":null,"abstract":"This new architecture for wireless power and data telemetry recovers power and system clock from a weak incident RF signal. An efficient RF-DC converter rectifies and multiplies the received signal, generating a practical DC voltage, far higher than the incident RF signal amplitude, increasing the range between the base station and the transponder. An injection locked LC oscillator recovers the system clock from the incident signal. Super-harmonic or sub-harmonic locking facilitates the separation of the incident and telemetry frequency without the need for a PLL. Experimental data from a 900 MHz transponder and a remotely powered 2.3 GHz wireless temperature sensor are presented. Both prototypes, implemented in 0.25 /spl mu/m CMOS, occupy less that 1 mm/sup 2/.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115446930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Sano, K. Murata, H. Fukuyama, S. Tsunashima, K. Ishii, K. Kurishima, H. Matsuzaki, T. Enoki, M. Tokumitsu, H. Sugahara, M. Muraguchi
{"title":"InP-based optical system ICs operating at 40 Gbit/s and beyond","authors":"K. Sano, K. Murata, H. Fukuyama, S. Tsunashima, K. Ishii, K. Kurishima, H. Matsuzaki, T. Enoki, M. Tokumitsu, H. Sugahara, M. Muraguchi","doi":"10.1109/RFIC.2004.1320607","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320607","url":null,"abstract":"InP-based 40-Gbit/s optical system ICs are steadily progressing for the start-up of 40-Gbit/s optical systems. Also, InP-based ICs operating beyond 40 Gbit/s are being investigated for future post-40-Gbit/s optical systems. This paper describes our recent progress on InP-based ICs operating at 40 Gbit/s and beyond, which include optoelectronic (OE) ICs. In testing ICs beyond 40 Gbit/s and toward 100 Gbit/s, the absence of signal sources is becoming a critical issue. 100Gbit/s pulse-pattern generators, which are indispensable for investigating a variety of 100-Gbit/s ICs, are also presented.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"642 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129398647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Guang Chen, H. Feng, Haolu Xie, R. Zhan, Qiong Wu, X. Guan, A. Wang, K. Takasuka, S. Tamura, Zhihua Wang, Chun Zhang
{"title":"RF characterization of ESD protection structures [RFIC applications]","authors":"Guang Chen, H. Feng, Haolu Xie, R. Zhan, Qiong Wu, X. Guan, A. Wang, K. Takasuka, S. Tamura, Zhihua Wang, Chun Zhang","doi":"10.1109/RFIC.2004.1320628","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320628","url":null,"abstract":"ESD (electrostatic discharge) protection design for RF ICs is a challenging design problem. This paper reports a comprehensive RF characterization of various RF ESD protection structures, including S-parameters, parasitic capacitance and resistance. It is found that a dual-direction SCR type ESD protection structure is the best RF ESD protection solution and an optimized two/three-diode string is an attractive solution as well. A new optimization parameter, F-factor, is introduced to evaluate the overall performance of RF ESD protection structures. A dual-SCR structure of 257 /spl mu/m/sup 2/ for 2 kV ESD protection features 43.2 fF parasitic capacitance at 2.4 GHz and F=180. This work is conducted using a commercial 0.35 /spl mu/m BiCMOS technology.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131013387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A novel superharmonic coupling topology for quadrature oscillator design at 6 GHz","authors":"T. Hancock, Gabriel M. Rebeiz","doi":"10.1109/RFIC.2004.1320597","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320597","url":null,"abstract":"This paper presents the design and measurement of a quadrature voltage controlled oscillator (VCO) at 6 GHz in a SiGe process. Phase quadrature is achieved by using a novel coupling scheme that is area efficient, does not increase power consumption and decreases the phase-noise by 3 dB. The QVCO has a 24% tuning range with a maximum output frequency of 5.92 GHz and an average output power of -5.3 dBm. The QVCO is compact, occupying an area of only 810 /spl mu/m/spl times/485 /spl mu/m without pads. A single VCO, identical to the core of the QVCO, was also designed and measured for comparison.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130614855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A low-power 10 Gb/s AGC optical postamplifier in SiGe","authors":"D. Kucharski, K. Kornegay","doi":"10.1109/RFIC.2004.1320514","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320514","url":null,"abstract":"A 10 Gb/s automatic gain control amplifier for use in optical receivers was implemented in a SiGe process with f/sub T/=45 GHz. Active peaking techniques were used to achieve a maximum gain of 48 dB with 7.8 GHz of bandwidth. The amplifier demonstrates less than 0.5 dB of peak-to-peak output amplitude variation over a 50 dB input amplitude range. It consumes 30 mW of power from a 3.3 V supply and remains functional at voltages as low as 2.7 V. The amplifier core occupies 0.1 mm/sup 2/ and requires no external components.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122666932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Kunihiro, S. Yamanouchi, T. Miyazaki, Y. Aoki, K. Ikuina, T. Ohtsuka, H. Hida
{"title":"A diplexer-matching dual-band power amplifier LTCC module for IEEE 802.11a/b/g wireless LANs","authors":"K. Kunihiro, S. Yamanouchi, T. Miyazaki, Y. Aoki, K. Ikuina, T. Ohtsuka, H. Hida","doi":"10.1109/RFIC.2004.1320603","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320603","url":null,"abstract":"We have developed a compact dual-band (2.4/5 GHz) power-amplifier module with a concurrent two-stage InGaP/GaAs HBT for triple-mode (IEEE 802.11a/b/g) WLANs. The proposed diplexer-matching network is three-dimensionally implemented in an LTCC substrate (5/spl times/5 mm). The module exhibits an output power of 20 dBm at 2.4 GHz, and 18 dBm at 5.25 GHz with an error vector magnitude of 4-5% for a 54-Mbps OFDM signal. Our approach of using a concurrent dual-band PA reduces the size and cost by almost half compared with using a conventional parallel PA.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122622421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Silicon ICs for high-speed, high-bandwidth optical data communications","authors":"M. Oprysko","doi":"10.1109/RFIC.2004.1320510","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320510","url":null,"abstract":"A wide range of silicon ICs have been demonstrated for high-speed, high-bandwidth optical data communications. These include a 12-channel VCSEL array driver at 10.3125 Gbps per channel for box/board level interconnects, a 7-tap distributed transversal filter for LAN/SAN interconnects, OC-768 receiver and transmitter for NVAN/MAN/Campus interconnects, and exploratory silicon 10 Gbps photodetectors for potential integration with logic circuits. In addition, high-speed circuits, >100 Gbps, and parallel array testers have been demonstrated to facilitate both high-speed and massively parallel optical link evaluation.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128915946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}