Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future最新文献

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A World Wide Web based architecture for the implementation of a virtual laboratory 基于万维网的虚拟实验室体系结构的实现
Francisco J. Gómez-Arribas, Manuel Cervera, Javier Martínez
{"title":"A World Wide Web based architecture for the implementation of a virtual laboratory","authors":"Francisco J. Gómez-Arribas, Manuel Cervera, Javier Martínez","doi":"10.1109/EURMIC.2000.874400","DOIUrl":"https://doi.org/10.1109/EURMIC.2000.874400","url":null,"abstract":"The World Wide Web (WWW) has given universities the opportunity to create a virtual laboratory based in remote controlled instrumentation. The solution proposed in the paper allows remote access to equipment, in such a way that is very similar to using the same equipment when performing real device measurements in a laboratory. An improved architecture simplifies the implementation of a virtual laboratory and allows a more versatile and efficient environment aimed at distance learning.","PeriodicalId":138250,"journal":{"name":"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123654398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Designing high speed asynchronous pipelines 设计高速异步管道
S. Perri, P. Corsonello, G. Cocorullo
{"title":"Designing high speed asynchronous pipelines","authors":"S. Perri, P. Corsonello, G. Cocorullo","doi":"10.1109/EURMIC.2000.874658","DOIUrl":"https://doi.org/10.1109/EURMIC.2000.874658","url":null,"abstract":"Usually, realizing self-timed pipelined data-paths for high performance Digital Signal Processors (DSPs) dynamic CMOS logic is used. In this paper a novel methodology to implement computational elements of self-timed data-paths is presented. It is based on the use of both static and dynamic CMOS modules. The former act as overlapped execution circuits and they anticipate their computation with respect to the dynamic blocks. The above method applied to a 32-bit addition stage allows a performance gain to be obtained of up to about 40% and a reduction in power dissipation of about 33%, with a reasonable area overhead compared to conventional design.","PeriodicalId":138250,"journal":{"name":"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123677863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Using rising pitch as a communication metaphor: an empirical investigation 运用上升音调作为交际隐喻:一项实证研究
D. Rigas, J. Alty
{"title":"Using rising pitch as a communication metaphor: an empirical investigation","authors":"D. Rigas, J. Alty","doi":"10.1109/EURMIC.2000.874497","DOIUrl":"https://doi.org/10.1109/EURMIC.2000.874497","url":null,"abstract":"The paper describes a series of experiments in which the possibility of using rising pitch as a communication metaphor in user interfaces is investigated. These experiments were performed with one and two sequences of rising pitch notes taken either from the Diatonic or the Chromatic scale. Two groups of subjects participated in these experiments. One group consisted of British origin subjects and the second group of international origin subjects. The two groups of subjects aimed to identify cultural differences in subjects' perception of rising (ascending) pitch and synthesised voices (musical instruments). Results indicated that rising pitch can be perceived by subjects and thus can be used to communicate certain types of information with a reasonable degree of accuracy (/spl plusmn/3). All results were significant statistically. For example, information to be communicated using this rising pitch approach could be length, spatial location, lists and many other user interface or multimedia events. Cultural background did not appear to influence perception of rising pitch sequences. The change of the instrument also did not influence the perception of users. The paper concludes with a series of empirically derived design guidelines for the use of rising pitch in auditory and multimedia systems.","PeriodicalId":138250,"journal":{"name":"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121435822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
SystemC based hardware synthesis becomes reality 基于SystemC的硬件综合成为现实
Heinz-Josef Schlebusch
{"title":"SystemC based hardware synthesis becomes reality","authors":"Heinz-Josef Schlebusch","doi":"10.1109/EURMIC.2000.874663","DOIUrl":"https://doi.org/10.1109/EURMIC.2000.874663","url":null,"abstract":"Summary form only given. The advances in ASIC technology have enabled the design of systems-on-chip (SoC). The complexity associated with SoC is creating many new challenges at all levels of the design process. The article discusses SystemC, an open community C++ modeling platform for system-level design and hardware/software co-design. SystemC is broadly supported by a large and growing number of leading system houses, semiconductor companies, intellectual property (IP) providers, embedded systems and EDA tool vendors through the Open SystemC Initiative (OSCI). The objective of the OSCI is to engender a whole new market for system-level design solutions, based on its support of SystemC and a common modeling platform with built-in interoperability. In order to gain acceptance from the SoC engineering community, the new standard modeling platform has to be more than just a means of communication; it has to support all kinds of features that can help to solve their most burning issue, namely \"time-to-market\". For SoC, it is essential to support the reuse of intellectual property (IP) for multiple designs. That in turn means the support of IP creation as well as IP integration. Until recently, the synthesis tools required VHDL/Verilog descriptions as the design entry language, which of course was one good reason for hardware engineers not to adopt SystemC in their design flow. In June 2000, Synopsys introduced SystemC Compiler, a synthesis tool that allows one to synthesise hardware IP from a synthesizable subset of SystemC, thereby removing one of the biggest hurdles for the adoption of SystemC by the hardware design community.","PeriodicalId":138250,"journal":{"name":"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128481341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Verifying sequence and content for safety critical hypermedia systems 验证安全关键超媒体系统的序列和内容
R. Newman
{"title":"Verifying sequence and content for safety critical hypermedia systems","authors":"R. Newman","doi":"10.1109/EURMIC.2000.874408","DOIUrl":"https://doi.org/10.1109/EURMIC.2000.874408","url":null,"abstract":"There is an increasing interest in the use of hypermedia for technical documentation systems. Where these systems are used in safety critical industries the design quality of the hypermedia product is of primary importance, since errors in presentation can cause errors in maintenance procedures, which in turn can cause malfunction of safety critical equipment. For this reason it is necessary to develop rigorous design methods which can offer guarantees of correctness. This paper extends previous work on this topic. The earlier work discussed a technique which allowed designers' storyboards to be translated into a process algebra specification-'formal storyboards'-allowing safety properties concerning sequence of presentation to be demonstrated. This technique was not applicable to the content of the presentation. This paper shows how the method may be combined with state based formal methods to provide a means of formal verification of the content as well.","PeriodicalId":138250,"journal":{"name":"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126355499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Simulation meets verification-checking temporal properties in SystemC 仿真满足验证-检查SystemC中的时间属性
D. W. Hoffmann, Jürgen Ruf, T. Kropf, W. Rosenstiel
{"title":"Simulation meets verification-checking temporal properties in SystemC","authors":"D. W. Hoffmann, Jürgen Ruf, T. Kropf, W. Rosenstiel","doi":"10.1109/EURMIC.2000.874664","DOIUrl":"https://doi.org/10.1109/EURMIC.2000.874664","url":null,"abstract":"Due to the increasing complexity of VLSI circuit designs, errors are likely to happen at all stages in the design cycle. Already today, more then 70% of the development time is spend on circuit debugging. This number is even expected to grow in future and imposes yet unsolved challenges on tomorrow's EDA industry. Therefore, the verification of systems (hardware or embedded hardware/software systems) is one of the most important tasks in the design process. To cope with the increasing complexity, various attempts have been made to increase productivity. Among those, one is to provide better suited system description languages (SDLs) supporting the designer at all levels of abstraction. Another important issue is the development of tailored validation and verification techniques. In the past, most verification techniques have been based on simulation and test methods. Recently, formal methods such as temporal property checking has become increasingly popular. However, their industrial applicability is currently restricted to small or medium sized design or to a specific phase in the design cycle. The author describe a simulation based method for verifying temporal properties of systems described in SystemC/sup TM/. The method allows the user to specify properties about the system in a finite version of linear time temporal logic (FLTL). These properties are then checked on-the-fly during each simulation run, and each violation is immediately signaled to the designer.","PeriodicalId":138250,"journal":{"name":"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125341946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Computer models for strategic business process optimisation 战略业务流程优化的计算机模型
V. Haase
{"title":"Computer models for strategic business process optimisation","authors":"V. Haase","doi":"10.1109/EURMIC.2000.874426","DOIUrl":"https://doi.org/10.1109/EURMIC.2000.874426","url":null,"abstract":"Classical models of economic processes are hampered by the fact that crisp mathematical formulae seldom exist, as human behaviour does not follow differential equations, and optimisation of strategic decision making is difficult for managers when business information systems confront them with megabytes of data to study. The concepts of the balanced scorecard and of decision support systems based on fuzzy logic are combined into a methodology and a software tool that is able to help executives to optimise their strategic business processes. The tool, ActiveScoreCard is used successfully by the Austrian Research Centers.","PeriodicalId":138250,"journal":{"name":"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114547907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
On the computation time of three-dimensional digital waveguide mesh acoustic models 三维数字波导网格声学模型的计算时间研究
G. Campos, D. Howard
{"title":"On the computation time of three-dimensional digital waveguide mesh acoustic models","authors":"G. Campos, D. Howard","doi":"10.1109/EURMIC.2000.874498","DOIUrl":"https://doi.org/10.1109/EURMIC.2000.874498","url":null,"abstract":"After briefly discussing the accuracy requirements of various auralisation system applications, the paper reviews the principles of digital-waveguide modelling and its application to 3D acoustic simulation for accurate auralisation. A formula is derived for the computation time of a regular rectilinear mesh model, assuming lossless propagation. A software implementation of this model is described along with the results from single-processor benchmarking tests. A parallelisation strategy applicable to both multiprocessor computers and workstation clusters is then presented and its impact on computation time analysed.","PeriodicalId":138250,"journal":{"name":"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126808695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Developing ICU-Talk. A computer based communication aid for patients in intensive care ICU-Talk发展。一种用于重症监护病人的计算机通信辅助设备
A. Judson, I. Ricketts, A. Waller, N. Alm, B. Gordon, F. MacAulay, J. Brodie, M. Etchels, A. Warden, A. J. Shearer
{"title":"Developing ICU-Talk. A computer based communication aid for patients in intensive care","authors":"A. Judson, I. Ricketts, A. Waller, N. Alm, B. Gordon, F. MacAulay, J. Brodie, M. Etchels, A. Warden, A. J. Shearer","doi":"10.1109/EURMIC.2000.874508","DOIUrl":"https://doi.org/10.1109/EURMIC.2000.874508","url":null,"abstract":"The paper highlights the development of a computerised communication aid for intubated patients in an Intensive Care Unit (ICU). Intubated patients in ICU have few methods of communicating other than attempting to mouth words and use gestures. Communication aids that are available, such as symbol charts and alphabet boards, unfortunately have not been designed to meet the specific requirements of these patients. Even these methods are not ideal for the patient, their family members or the staff caring for the patient. From previous research studies of communication within ICU, patients often feel disempowered and depressed due their inability to contribute to conversations. This often leads to feelings of social isolation. ICU-Talk will be developed to allow the patient to have more control of their communications and at the same time address their ongoing problems and needs on an individual basis.","PeriodicalId":138250,"journal":{"name":"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125739355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Verification of designs containing black boxes 验证包含黑盒的设计
Wolfgang Günther, Nicole Drechsler, R. Drechsler, B. Becker
{"title":"Verification of designs containing black boxes","authors":"Wolfgang Günther, Nicole Drechsler, R. Drechsler, B. Becker","doi":"10.1109/EURMIC.2000.874621","DOIUrl":"https://doi.org/10.1109/EURMIC.2000.874621","url":null,"abstract":"Often modern designs contain regions where the implementation of certain components is not (fully) known. These regions are called black boxes in the following. They occur e.g. if different designers work on a project in parallel or if IP cores are used. An approach based on a symbolic representation of characteristic functions for verifying circuits with black boxes is presented. We show that by this method more faults can be detected than with pure binary simulation and symbolic simulation using BDDs, respectively, only. This results from the formulation of our algorithm that allows implications over the black box. Experimental results are given to show what parts of a design can be proven to be correct, if black boxes are assumed. Of course, the probability for the detection of a fault in general depends on the size of the unknown regions. But fault injection experiments on benchmarks show that for many circuits, even up to 90% of the faults are detected, even though large parts of the design are unspecified.","PeriodicalId":138250,"journal":{"name":"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127033345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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