Simulation meets verification-checking temporal properties in SystemC

Abstract

Due to the increasing complexity of VLSI circuit designs, errors are likely to happen at all stages in the design cycle. Already today, more then 70% of the development time is spend on circuit debugging. This number is even expected to grow in future and imposes yet unsolved challenges on tomorrow's EDA industry. Therefore, the verification of systems (hardware or embedded hardware/software systems) is one of the most important tasks in the design process. To cope with the increasing complexity, various attempts have been made to increase productivity. Among those, one is to provide better suited system description languages (SDLs) supporting the designer at all levels of abstraction. Another important issue is the development of tailored validation and verification techniques. In the past, most verification techniques have been based on simulation and test methods. Recently, formal methods such as temporal property checking has become increasingly popular. However, their industrial applicability is currently restricted to small or medium sized design or to a specific phase in the design cycle. The author describe a simulation based method for verifying temporal properties of systems described in SystemC/sup TM/. The method allows the user to specify properties about the system in a finite version of linear time temporal logic (FLTL). These properties are then checked on-the-fly during each simulation run, and each violation is immediately signaled to the designer.