Designing high speed asynchronous pipelines

Usually, realizing self-timed pipelined data-paths for high performance Digital Signal Processors (DSPs) dynamic CMOS logic is used. In this paper a novel methodology to implement computational elements of self-timed data-paths is presented. It is based on the use of both static and dynamic CMOS modules. The former act as overlapped execution circuits and they anticipate their computation with respect to the dynamic blocks. The above method applied to a 32-bit addition stage allows a performance gain to be obtained of up to about 40% and a reduction in power dissipation of about 33%, with a reasonable area overhead compared to conventional design.