{"title":"Degradation in TDDB of Cu/low-k test structures due to field interaction between adjacent metal lines","authors":"R. X. Ong, C. Gan, T. L. Tan","doi":"10.1109/IRPS.2013.6532055","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532055","url":null,"abstract":"In this paper, small area test structures were used to study the effect of field interaction between neighboring fingers of the test structures. Time dependent dielectric breakdown tests were performed on the test structures. It was determined that the electric field between adjacent fingers, and not only the electric field between the cathode and anode, has an impact on the breakdown lifetime of the low-k dielectric.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131228922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A physics-based compact model for SCR devices used in ESD protection circuits","authors":"R. Mertens, E. Rosenbaum","doi":"10.1109/IRPS.2013.6531947","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531947","url":null,"abstract":"A CMOS SCR compact model is developed for circuit simulation of ESD protection circuits. The model is comprised of coupled NPN and PNP transistors. A previously unnoted interaction between these transistors is described, resulting in improved agreement between simulation and measurement. This model addresses fundamental limitations of previous models, allowing for improved simulation accuracy, while limiting the number of parameters. The model parameters are scalable with respect to the layout spacings.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131457985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Long, X. Lian, C. Cagli, L. Perniola, E. Miranda, D. Jiménez, H. Lv, Qi Liu, Ling Li, Z. Huo, Ming Liu, J. Suñé
{"title":"Compact analytical models for the SET and RESET switching statistics of RRAM inspired in the cell-based percolation model of gate dielectric breakdown","authors":"S. Long, X. Lian, C. Cagli, L. Perniola, E. Miranda, D. Jiménez, H. Lv, Qi Liu, Ling Li, Z. Huo, Ming Liu, J. Suñé","doi":"10.1109/IRPS.2013.6532023","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532023","url":null,"abstract":"In this work, we depart from the cell-based percolation model of gate dielectric breakdown (BD) to propose analytical models for the SET and RESET statistics in resistive switching memory (RRAM). The SET or RESET statistics model consists of two basic elements: (i) a cell-based geometrical model to describe the dependence of the resistive switching (RS) distribution on the defect generation in the conductive filament (CF), and (ii) a deterministic model for the SET/RESET dynamics to describe the relation of the defect generation with measurable variables such as the SET/RESET voltage and current. The experimental observations in HfO2- and NiO-based RRAM devices can be successfully accounted for by our models for RS statistics. The models set a framework for the consideration of performance-reliability tradeoffs in RRAM.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"24 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132357583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kyongtaek Lee, Wonchang Kang, Eun-ae Chung, Gunrae Kim, H. Shim, Hyunwoo Lee, Hyejin Kim, M. Choe, N. Lee, Anuj Patel, Junekyun Park, Jongwoo Park
{"title":"Technology scaling on High-K & Metal-Gate FinFET BTI reliability","authors":"Kyongtaek Lee, Wonchang Kang, Eun-ae Chung, Gunrae Kim, H. Shim, Hyunwoo Lee, Hyejin Kim, M. Choe, N. Lee, Anuj Patel, Junekyun Park, Jongwoo Park","doi":"10.1109/IRPS.2013.6531956","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531956","url":null,"abstract":"High-K (HK) & Metal-Gate (MG) transistor technology have become a mainstream for the logic & SOC processes. On HK/MG process, bias-temp instability (BTI) poses continuous challenges on the technology scaling despite the reduced Vcc. In recent technologies, PMOS NBTI degradation is increased while NMOS PBTI was reduced with HK scaling. Interfacial Layer (IL) scaling underneath the HK that affects PMOS NBTI and device performance is very challenging. Impact of technology scaling on BTI and BTI on FinFET technology is discussed.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"207 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121275496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Duty-cycle shift under asymmetric BTI aging: A simple characterization method and its application to SRAM timing","authors":"Xiaofei Wang, J. Keane, P. Jain, V. Reddy, C. Kim","doi":"10.1109/IRPS.2013.6532007","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532007","url":null,"abstract":"The effect of DC BTI stress on the clock signal's duty-cycle has been experimentally verified for the first time based on the precise frequency shift measurement from Ring OSCillators (ROSC). A simple and practical methodology based on the “silicon odometer” beat-frequency detection framework has been proposed for accurately measuring duty-cycle shifts while preventing unwanted BTI recovery. The measurement results from a 65nm test chip were used to further analyze the impact of asymmetric BTI aging during clock gated mode on SRAM timing signals.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128140421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Stress-induced-voiding risk factor and stress migration model for Cu interconnect reliability","authors":"H. Yao, P. Justison, J. Poppe","doi":"10.1109/IRPS.2013.6531955","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531955","url":null,"abstract":"SM reliability data have been treated qualitatively to define pass or fail criteria in the past. However, realistic quantitative stress-induced-voiding (SIV) risk analysis and lifetime estimates for products were not available due to lack of quantitative data and a suitable SM model. In this paper, we provide quantitative analysis of SIV risk based on geometry factors and further establish a comprehensive SM model for SM lifetime estimation for 32nm technology and beyond. An SIV risk factor is defined to quantify the relative risks of Cu BEOL interconnect structures. Based on the new SM model, an effective geometry factor was found for an accelerated SM test method to perform SM lifetime estimation from measurable SM data.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"603 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134173354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Debecker, K. Vanstreels, M. Gonzalez, B. Vandevelde
{"title":"Delamination in BEOL: Analysis of interface failure by combined experimental & modeling approaches","authors":"B. Debecker, K. Vanstreels, M. Gonzalez, B. Vandevelde","doi":"10.1109/IRPS.2013.6532031","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532031","url":null,"abstract":"It is demonstrated that the widely used equation to derive the adhesive strength from the external load in a 4 point bending test has a certain error by taking only the substrate's elastic parameters into account. Next to this, failure location analysis gives insight on the measured variation of adhesive strength for the same interface. Subsequently, with numerical simulations, the adhesive strength can be separated in its different energy modes, allowing a better understanding and characterization of the experimental observations (e.g. higher cohesive energy for increasing low-k stiffness). Finally, the competing failure mechanisms within the BEOL are identified as necessary qualifiers for BEOL failure assessment, where currently adhesion strength is mainly used for ranking the performance of different BEOL interfaces.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134255185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Amoroso, L. Gerrer, F. Adamu-Lema, S. Markov, A. Asenov
{"title":"Impact of statistical variability and 3D electrostatics on post-cycling anomalous charge loss in nanoscale Flash memories","authors":"S. Amoroso, L. Gerrer, F. Adamu-Lema, S. Markov, A. Asenov","doi":"10.1109/IRPS.2013.6531980","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531980","url":null,"abstract":"This paper presents a detailed simulation investigation of the impact of statistical variability and 3D electrostatics on SILC distribution in nanoscale Flash memories. Considering a 1-TAT model we study the SILC statistics under stationary and dynamic retention conditions. Our results show that SILC is dispersed over the channel area due to non-uniform electrostatics in nanoscale devices. Further, the floating gate poly-silicon granularity plays a major role in determining the SILC distribution, depending on the gate polarity. Dynamic charge loss simulations highlight that the impact of 3D electrostatics is dominant over the cell-to-cell variability. Finally, we analyze the electron emission statistics on a single cell, showing that this gives rise to a lower SILC dispersion than an analytical Poisson charge loss statistics. Our results are fundamental to determine the degree of accuracy of 1D models for the post-cycling charge loss statistics simulation in nanoscale Flash memories.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133358989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jaewook Yang, Wonhyo Cha, S. Seo, H. Oh, J. Oh, H. Shim, Se-Kyung Choi, Byungkook Kim, Seokwon Cho, Kiseog Kim, K. Ahn, G. Bae
{"title":"The effect of hydrogen on program disturbance in sub-2ynm Nand flash","authors":"Jaewook Yang, Wonhyo Cha, S. Seo, H. Oh, J. Oh, H. Shim, Se-Kyung Choi, Byungkook Kim, Seokwon Cho, Kiseog Kim, K. Ahn, G. Bae","doi":"10.1109/IRPS.2013.6532092","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532092","url":null,"abstract":"The Effect of hydrogen on program disturbance in sub-2ynm NAND flash is studied. It is supposed that boron atoms implanted for field stop are deactivated due to the formation of neutral boron-hydrogen pair. Boron deactivation results in the degradation of STI leakage and program disturbance. By adopting hydrogen reducing process, program disturbance of 2ynm NAND flash is successfully improved.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130349653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Challenges in the characterization and modeling of BTI induced variability in metal gate / High-k CMOS technologies","authors":"A. Kerber, T. Nigam","doi":"10.1109/IRPS.2013.6531959","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531959","url":null,"abstract":"Large scale BTI data was collected on discrete MG/HK devices to discuss modeling challenges related to BTI induced variability. A fast, parallel BTI testing procedure is introduced. This utilizes the PCI card characterization methodology to highlight a close link between BTI variability and RDF, and to discuss the impact of BTI recovery and wafer-to-wafer variation on the BTI statistics. We demonstrate a correlation between time-zero VT and ΔVT and illustrate the minor impact of BTI induced variability on post-stress VT distributions relevant for modeling the circuit aging.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124885581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}