Challenges in the characterization and modeling of BTI induced variability in metal gate / High-k CMOS technologies

Abstract

Large scale BTI data was collected on discrete MG/HK devices to discuss modeling challenges related to BTI induced variability. A fast, parallel BTI testing procedure is introduced. This utilizes the PCI card characterization methodology to highlight a close link between BTI variability and RDF, and to discuss the impact of BTI recovery and wafer-to-wafer variation on the BTI statistics. We demonstrate a correlation between time-zero VT and ΔVT and illustrate the minor impact of BTI induced variability on post-stress VT distributions relevant for modeling the circuit aging.