13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)最新文献

Design of a High-Speed Asynchronous Turbo Decoder 高速异步Turbo解码器的设计

13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07) Pub Date : 2007-03-12 DOI: 10.1109/ASYNC.2007.16

P. Golani, G. Dimou, M. Prakash, P. Beerel

{"title":"Design of a High-Speed Asynchronous Turbo Decoder","authors":"P. Golani, G. Dimou, M. Prakash, P. Beerel","doi":"10.1109/ASYNC.2007.16","DOIUrl":"https://doi.org/10.1109/ASYNC.2007.16","url":null,"abstract":"This paper explores the advantages of high performance asynchronous circuits in a semi-custom standard cell environment for high-throughput turbo coding. Turbo codes are high-performance error correction codes used in applications where maximal information transfer is needed over a limited-bandwidth communication link in the presence of data corrupting noise. Specifically we designed an asynchronous high-speed turbo decoder that can be potentially used for new wireless communications protocols with close to OC-12 throughputs. The design has been implemented using a new static single-track-full-buffer (SSTFB) standard cell library in IBM 0.18 mum technology that provides low latency, fast cycle-time, and more robustness to noise than previously studied single-track full-buffer technology (STFB). A high-speed synchronous counterpart using the same high-speed architecture is designed in the same technology for comparison. The results demonstrate that for a variety of network constraints, the asynchronous design provides advantages in throughput per area. Moreover, the asynchronous design can support very low-latency network constraints not achievable with the synchronous alternative.","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121436183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Demystifying Data-Driven and Pausible Clocking Schemes 揭开数据驱动和可调时钟方案的神秘面纱

13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07) Pub Date : 2007-03-12 DOI: 10.1109/ASYNC.2007.15

R. Mullins, S. Moore

引用次数: 72

A Jitter Attenuating Timing Chain 抖动衰减时序链

13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07) Pub Date : 2007-03-12 DOI: 10.1109/ASYNC.2007.8

Suwen Yang, M. Greenstreet, Jihong Ren

引用次数: 4

High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link 高速率波管道异步片上位串行数据链

13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07) Pub Date : 2007-03-12 DOI: 10.1109/ASYNC.2007.20

R. Dobkin, Y. Perelman, T. Liran, R. Ginosar, A. Kolodny

引用次数: 40

On-chip samplers for test and debug of asynchronous circuits 用于异步电路测试和调试的片上采样器

13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07) Pub Date : 2007-03-12 DOI: 10.1109/ASYNC.2007.24

Frankie Y. Liu, R. Ho, R. Drost, Scott M. Fairbanks

引用次数: 3

Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip 用异步片上网络的CADP图示正式验证CHP规格

13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07) Pub Date : 2007-03-12 DOI: 10.1109/ASYNC.2007.18

Gwen Salaün, Wendelin Serwe, Y. Thonnart, P. Vivet

引用次数: 35

The Design of a Genetic Muller C-Element 遗传Muller c -元的设计

13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07) Pub Date : 2007-03-12 DOI: 10.1109/ASYNC.2007.27

Nam-Phuong D. Nguyen, Hiroyuki Kuwahara, C. Myers, J. Keener

引用次数: 24

A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability 一种考虑过程可变性的高分辨率闪存时间-数字转换器

13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07) Pub Date : 2007-03-12 DOI: 10.1109/ASYNC.2007.7

N. Minas, D. Kinniment, K. Heron, G. Russell

引用次数: 22

Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication 用于两相延迟不敏感全局通信的高效异步协议转换器

13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07) Pub Date : 2007-03-12 DOI: 10.1109/ASYNC.2007.17

Amit Mitra, William F. McLaughlin, S. Nowick

{"title":"Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication","authors":"Amit Mitra, William F. McLaughlin, S. Nowick","doi":"10.1109/ASYNC.2007.17","DOIUrl":"https://doi.org/10.1109/ASYNC.2007.17","url":null,"abstract":"As system-level interconnect incurs increasing penalties in latency, round-trip cycle time and power, and as timing-variability becomes an increasing design challenge, there is renewed interest in using two-phase delay-insensitive protocols for global system-level communication. However, in practice, when designing asynchronous systems, it is extremely inefficient to build local computation nodes with two-phase logic, hence four-phase computation blocks are typically used. This paper proposes a new architecture, and circuit-level implementations, for a family of asynchronous protocol converters, which efficiently convert between two- and four-phase protocols, thus facilitating system design with robust global two-phase protocols and local four-phase protocols. The main focus is on a level-encoded dual-rail (LEDR) two-phase protocol for global communication, and a four-phase return-to-zero (RZ) protocol for asynchronous computation blocks. However, with small modifications, the converters are extended to handle other common four-phase protocols, such as 1- of-4 and single-rail bundled data. The converters are highly robust, with almost entirely quasi delay- insensitive implementations, yet exhibit high performance and modest area overhead. Initial post-layout simulations in a 0.18 micron TSMC process are provided, both assuming a small computation block (8times8 combinational multiplier) as well as an empty computation block (FIFO stage).","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124912471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

A Cycle-Based Decomposition Method for Burst-Mode Asynchronous Controllers 突发模式异步控制器的循环分解方法

13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07) Pub Date : 2007-03-12 DOI: 10.1109/ASYNC.2007.6

Melinda Y. Agyekum, S. Nowick

{"title":"A Cycle-Based Decomposition Method for Burst-Mode Asynchronous Controllers","authors":"Melinda Y. Agyekum, S. Nowick","doi":"10.1109/ASYNC.2007.6","DOIUrl":"https://doi.org/10.1109/ASYNC.2007.6","url":null,"abstract":"In this paper, a systematic and automated methodology is proposed for decomposing an asynchronous burst-mode (BM) controller into smaller sub-controllers, where each resulting sub-controller is activated on a communication channel. The proposed approach consists of a new decomposition algorithm, control micro-architecture and inter-controller communication protocol. This method has also been broadened to handle extended burst- mode (XBM) controllers. For both controller types, only a moderate amount of auxiliary hardware is required, and optimizations are proposed to eliminate or simplify this hardware. Initial runtime results for both burst-mode and extended burst- mode controllers are promising. Two of the largest BM benchmarks (dean-cache, scsi) were run using the Minimalist CAD tool and an optimized script. While the original controllers each timed out after 10 hours, the decomposition runs each completed in under 84 seconds. Further attempts to synthesize the original controllers using a suboptimal script succeeded, but with 16-200x greater runtime. Several XBM benchmarks were synthesized using the 3D CAD tool; one large complex controller (cdp-pl) was unable to complete while the decomposed run succeeded in under 197 seconds.","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127262125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4