On-chip samplers for test and debug of asynchronous circuits

Abstract

On-chip high-bandwidth sampling circuits supplement traditional test and debug techniques by non-invasively probing analog voltages for off-chip measurement. Existing circuits rely on sub-sampling techniques and thus require a synchronous clock. We extend these ideas to asynchronous circuits by combining an analog sampling head with a variable delay element and activating this circuit with an asynchronously triggered event. Repeated triggering events with different delays emulate sub-sampling. Simulations in a 180 nm technology of SRAM timing margins and GasP control failure modes show this technique can probe asynchronous signals with high fidelity.