{"title":"漩涡:一个超标量异步处理器","authors":"Andrew Lines","doi":"10.1109/ASYNC.2007.28","DOIUrl":null,"url":null,"abstract":"The \"Vortex\" processor is a general purpose CPU with a novel architecture and instruction set. The primary feature of the Vortex architecture is many parallel function units which communicate through a central crossbar, instead of a traditional register file. Instructions are fetched in parallel by cache lines, as in a VLIW processor, but any data or structural dependencies are resolved deterministically by the hardware, as in a superscalar processor. The prototype Vortex CPU supports a 32-bit integer datapath and executes up to 9 instructions per cycle. It uses the \"integrated pipelining\" asynchronous design style, was fabricated in 2001 in TSMC's 0.15 mum G process, and runs at a typical frequency of 475MHz. Although the Vortex CPU itself has not been commercialized, many of its component circuits have been used in the products of Fulcrum Microsystems.","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"The Vortex: A Superscalar Asynchronous Processor\",\"authors\":\"Andrew Lines\",\"doi\":\"10.1109/ASYNC.2007.28\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The \\\"Vortex\\\" processor is a general purpose CPU with a novel architecture and instruction set. The primary feature of the Vortex architecture is many parallel function units which communicate through a central crossbar, instead of a traditional register file. Instructions are fetched in parallel by cache lines, as in a VLIW processor, but any data or structural dependencies are resolved deterministically by the hardware, as in a superscalar processor. The prototype Vortex CPU supports a 32-bit integer datapath and executes up to 9 instructions per cycle. It uses the \\\"integrated pipelining\\\" asynchronous design style, was fabricated in 2001 in TSMC's 0.15 mum G process, and runs at a typical frequency of 475MHz. Although the Vortex CPU itself has not been commercialized, many of its component circuits have been used in the products of Fulcrum Microsystems.\",\"PeriodicalId\":136595,\"journal\":{\"name\":\"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)\",\"volume\":\"41 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-03-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASYNC.2007.28\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASYNC.2007.28","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The "Vortex" processor is a general purpose CPU with a novel architecture and instruction set. The primary feature of the Vortex architecture is many parallel function units which communicate through a central crossbar, instead of a traditional register file. Instructions are fetched in parallel by cache lines, as in a VLIW processor, but any data or structural dependencies are resolved deterministically by the hardware, as in a superscalar processor. The prototype Vortex CPU supports a 32-bit integer datapath and executes up to 9 instructions per cycle. It uses the "integrated pipelining" asynchronous design style, was fabricated in 2001 in TSMC's 0.15 mum G process, and runs at a typical frequency of 475MHz. Although the Vortex CPU itself has not been commercialized, many of its component circuits have been used in the products of Fulcrum Microsystems.