International Conference on Compilers, Architecture, and Synthesis for Embedded Systems最新文献_第3页

DaaC: device-reserved memory as an eviction-based file cache DaaC:设备预留的内存，作为基于驱逐的文件缓存

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems Pub Date : 2012-10-07 DOI: 10.1145/2380403.2380439

Jinkyu Jeong, Hwanju Kim, Jeaho Hwang, Joonwon Lee, S. Maeng

{"title":"DaaC: device-reserved memory as an eviction-based file cache","authors":"Jinkyu Jeong, Hwanju Kim, Jeaho Hwang, Joonwon Lee, S. Maeng","doi":"10.1145/2380403.2380439","DOIUrl":"https://doi.org/10.1145/2380403.2380439","url":null,"abstract":"Most embedded systems require contiguous memory space to be reserved for each device, which may lead to memory under-utilization. Although several approaches have been proposed to address this issue, they have limitations of either inefficient memory usage or long latency for switching the reserved memory space between a device and general-purpose uses.\u0000 Our scheme utilizes the reserved memory as an eviction-based file cache. It guarantees contiguous memory allocation to devices while providing idle device memory as an additional file cache called eCache for general-purpose usage. Since the eCache stores only evicted data from in-kernel page cache, memory efficiency is preserved and allocation time for devices is minimized. Cost-based region selection also alleviates additional read I/Os by carefully discarding cached data from the eCache. The prototype is implemented on the Nexus S smartphone and is evaluated with popular Android applications. The evaluation results show that 50%-85% of flash read I/Os are reduced and application launch performance is improved by 8%-16% while the reallocation time is limited to a few milliseconds.","PeriodicalId":136293,"journal":{"name":"International Conference on Compilers, Architecture, and Synthesis for Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130326740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Side channel attacks and the non volatile memory of the future 侧信道攻击和未来的非易失性存储器

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems Pub Date : 2012-10-07 DOI: 10.1145/2380403.2380413

Z. Dyka, C. Walczyk, D. Walczyk, C. Wenger, P. Langendörfer

引用次数: 4

Embedded reconfigurable architectures 嵌入式可重构架构

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems Pub Date : 2012-10-07 DOI: 10.1145/2380403.2380444

Stephan Wong

{"title":"Embedded reconfigurable architectures","authors":"Stephan Wong","doi":"10.1145/2380403.2380444","DOIUrl":"https://doi.org/10.1145/2380403.2380444","url":null,"abstract":"In current-day embedded systems design, one is faced with cut-throat competition to deliver new functionalities in increasingly shorter time frames. This is now achieved by incorporating processor cores into embedded systems through (re-)programmability. However, this is not always beneficial for the performance or energy consumption. Therefore, adaptable embedded systems have been proposed to deal with these negative effects by reconfiguring the critical sections of an embedded system. In these proposals, we are clearly witnessing a trend that is moving from static configurations to dynamic (re)configurations.\u0000 Consequently, the proposed embedded systems can adapt their functionality at run-time to meet the application(s) requirements (e.g., performance) while operating in different environments (e.g., power and hardware resources). Besides processor cores, we have to deal with memory hierarchies and network-on-chips that should also be (dynamically) reconfigurable. Furthermore, the interplay of these components is increasing the design complexity that can be only alleviated if they can self-optimize.\u0000 In this tutorial, we will present and discuss several strategies to perform the mentioned dynamic reconfiguration of the processor, memory, and NoC components - together with their interaction. We will review and present the state-of-the-art for the design of each component that allows for a gradual selection of design points in the trade-off between performance and power. Finally, we will highlight an open-source project that incorporates many approaches for dynamic reconfiguration in both actual hardware and simulation accompanied by the necessary tools.","PeriodicalId":136293,"journal":{"name":"International Conference on Compilers, Architecture, and Synthesis for Embedded Systems","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127210216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Automatic generation of hardware/software interfaces 自动生成硬件/软件接口

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems Pub Date : 2011-10-09 DOI: 10.1145/2038698.2038700

Arvind

引用次数: 4

Challenges for embedded multicore architecture 嵌入式多核架构的挑战

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems Pub Date : 2010-10-24 DOI: 10.1145/1878921.1878960

L. Carro, G. Gaydadjiev

引用次数: 0

E < MC2: less energy through multi-copy cache E < MC2:通过多副本缓存减少能量

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems Pub Date : 2010-10-24 DOI: 10.1145/1878921.1878956

Arup Chakraborty, H. Homayoun, A. Djahromi, N. Dutt, A. Eltawil, F. Kurdahi

引用次数: 43

Balancing memory and performance through selective flushing of software code caches 通过有选择地刷新软件代码缓存来平衡内存和性能

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems Pub Date : 2010-10-24 DOI: 10.1145/1878921.1878923

Apala Guha, K. Hazelwood, M. Soffa

{"title":"Balancing memory and performance through selective flushing of software code caches","authors":"Apala Guha, K. Hazelwood, M. Soffa","doi":"10.1145/1878921.1878923","DOIUrl":"https://doi.org/10.1145/1878921.1878923","url":null,"abstract":"Dynamic binary translators (DBTs) are becoming increasingly important because of their power and flexibility. However, the high memory demands of DBTs present an obstacle for all platforms, and especially embedded systems. The memory demand is typically controlled by placing a limit on cached translations and forcing the DBT to flush all translations upon reaching the limit. This solution manifests as a performance inefficiency because many flushed translations require retranslation. Ideally, translations should be selectively flushed to minimize retranslations for a given memory limit. However, three obstacles exist:(1) it is difficult to predict which selections will minimize retranslation,(2) selective flushing results in greater book-keeping overheads than full flushing, and(3) the emergence of multicore processors and multi-threaded programming complicates most flushing algorithms. These issues have led to the widespread adoption of full flushing as a standard protocol. In this paper, we present a partial flushing approach aimed at reducing retranslation overhead and improving overall performance, given a fixed memory budget. Our technique applies uniformly to single-threaded and multi-threaded guest applications","PeriodicalId":136293,"journal":{"name":"International Conference on Compilers, Architecture, and Synthesis for Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130368215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Improving scratchpad allocation with demand-driven data tiling 通过需求驱动的数据平铺改善便签簿分配

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems Pub Date : 2010-10-24 DOI: 10.1145/1878921.1878942

Xuejun Yang, Li Wang, Jingling Xue, T. Tang, Xiaoguang Ren, S. Ye

引用次数: 5

Mosaic of organic development through technology intervention in the rural indian context 技术干预下印度农村有机发展的马赛克

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems Pub Date : 2010-10-24 DOI: 10.1145/1878921.1878929

Rajeswari Pingali, P. Niranjana

引用次数: 0

Optimizing energy to minimize errors in dataflow graphs using approximate adders 使用近似加法器优化能量以最小化数据流图中的错误

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems Pub Date : 2010-10-24 DOI: 10.1145/1878921.1878948

Z. Kedem, V. Mooney, Kirthi Krishna Muntimadugu, K. Palem, Avani Devarasetty, Phani Deepak Parasuramuni

引用次数: 20