Gustavo A. Chaparro-Baquero, Shi Sha, Soamar Homsi, Wujie Wen, Gang Quan
{"title":"Thermal-aware joint CPU and memory scheduling for hard real-time tasks on multicore 3D platforms","authors":"Gustavo A. Chaparro-Baquero, Shi Sha, Soamar Homsi, Wujie Wen, Gang Quan","doi":"10.1109/IGCC.2017.8323573","DOIUrl":"https://doi.org/10.1109/IGCC.2017.8323573","url":null,"abstract":"Designing 3D systems with on-chip DRAM is a promising solution to improve memory bandwidth and reduce memory access latency. However, 3D chips exacerbate the chip thermal problem due to their longer heat dissipation path, as well as the tight thermal coupling between logic and memory layers. In this paper, we are interested in studying thermal aware resource management strategies for both CPUs and memory systems when realizing hard real-time systems on 3D platforms under given peak temperature constraints. Given the dramatically increased power density not only from CPUs but also from memory systems as well, we believe that a joint CPU and memory system resource management is highly desired for 3D platforms to effectively deal with the heat dissipation confined in a small package. In addition, different from many existing thermal management strategies, which are reactive and best-effort in nature, we are more interested in ones that can ensure the strong guarantee for real-time applications. To this end, we introduce a novel approach that incorporates the periodic resource model to guarantee timing constraints for hard real-time systems under thermal constraints. In the meantime, by periodically (deterministically) throttling the accesses of CPUs and memory resources, our approach can effectively guarantee the thermal constraints imposed on both CPUs and memory systems. We use simulation results to demonstrate the effectiveness of our proposed approach in guaranteeing both the timing and temperature constraints for hard real-time tasks on 3D platforms.","PeriodicalId":133239,"journal":{"name":"2017 Eighth International Green and Sustainable Computing Conference (IGSC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115573660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Energy efficiency analysis of query optimizations on MongoDB and Cassandra","authors":"Divya Mahajan, Ziliang Zong","doi":"10.1109/IGCC.2017.8323581","DOIUrl":"https://doi.org/10.1109/IGCC.2017.8323581","url":null,"abstract":"As big data emerges, the complexity of database workloads and database systems has increased significantly. It is no longer possible for one type of database to efficiently handle all big data applications. NoSQL databases are widely used to complement conventional SQL databases. In addition to traditional metrics such as response time and throughput, large scale NoSQL database systems pose higher requirements on energy efficiency due to the incredible volume of data (and the associated cost) that need to be stored and processed. Unfortunately, research on optimizations for energy efficiency in database systems has been historically overlooked. In this paper, we investigate numerous optimizations for two NoSQL databases (MongoDB and Cassandra) and conduct a comprehensive study on the impact of these optimizations on performance and energy efficiency. Our experimental results derived from 100GB of Twitter data reveal that 1) energy efficiency can be improved significantly for both MongoDB and Cassandra via query optimizations without degrading performance; and 2) energy efficiency does not always scale linearly with performance improvement.","PeriodicalId":133239,"journal":{"name":"2017 Eighth International Green and Sustainable Computing Conference (IGSC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115813905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Energy optimization for perpetual IoT networks of heterogeneous sensors","authors":"N. Alhassoun","doi":"10.1109/IGCC.2017.8323595","DOIUrl":"https://doi.org/10.1109/IGCC.2017.8323595","url":null,"abstract":"In our research we aim to handle energy limitations caused by perpetual operations in different IoT platforms, such as mission-critical and assisted living developments. IoT deployments hold significant promises to improve the quality of life; however, several limitations arise in operating IoT deployments in a scalable and resilient manner over time. Limitations include the divers nature of IoT settings and deployments, which play an important role in both the accuracy and cost of applications. In addition, IoT devices typically are small in size with restricted resources including limited compute power, battery and storage capabilities. Furthermore, assisted living and mission-critical systems are expected to operate 24/7 to monitor and detect critical events. This raises issues of the cost of operations and continuous energy consumptions. In our research, we are uniquely leveraging different concepts, such as activities of daily living (ADLs) and heterogeneity of IoT devices; to create perpetual IoT platforms by energy-optimized sensor activations.","PeriodicalId":133239,"journal":{"name":"2017 Eighth International Green and Sustainable Computing Conference (IGSC)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116236136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Muhammad Wajahat, Salman Masood, Abhinav Sau, Anshul Gandhi
{"title":"Lessons learnt from software tuning of a Memcached-backed, multi-tier, web cloud application","authors":"Muhammad Wajahat, Salman Masood, Abhinav Sau, Anshul Gandhi","doi":"10.1109/IGCC.2017.8323580","DOIUrl":"https://doi.org/10.1109/IGCC.2017.8323580","url":null,"abstract":"Cloud computing has largely replaced dedicated and physical computing systems by providing critical features such as elasticity and on-demand access to resources. However, despite its many benefits, the cloud does have its limitations, such as limited or no control over the hardware and limited customization options. Users who deploy applications on the cloud only have control over software tuning and optimizations since the infrastructure is managed by the provider. In this paper, we analyze cloud-deployed Web applications that are multi-tiered and employ Memcached as the object caching layer. Memcached is a high performance memory caching system and, if there are no other bottlenecks in the system, the overall application performance should be dictated by Memcached. However, we show that other components of the system such as web servers, load balancers, and some underlying system configurations, severely impact application performance. We analyze these components and provide guidelines on their implementation and parameter tuning to minimize resource waste in the cloud.","PeriodicalId":133239,"journal":{"name":"2017 Eighth International Green and Sustainable Computing Conference (IGSC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116498950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Donald Kline, Nikolas Parshook, A. Johnson, J. Stine, W. Stanchina, E. Brunvand, A. Jones
{"title":"Sustainable IC design and fabrication","authors":"Donald Kline, Nikolas Parshook, A. Johnson, J. Stine, W. Stanchina, E. Brunvand, A. Jones","doi":"10.1109/IGCC.2017.8323572","DOIUrl":"https://doi.org/10.1109/IGCC.2017.8323572","url":null,"abstract":"Low-energy computing in the use phase is compelling because it helps to address thermal density issues of deeply scaled CMOS, maximizes battery-life of mobile computing platforms, while also addressing sustainability. Unfortunately, environmental impacts of fabricating CMOS integrated circuits (ICs) is increasing and rapidly catching the operational phase of computing systems, particularly for low-energy and mobile computing products. This is due to trends in fabrication techniques for increasingly small geometries, such as increasing photo-lithography and metrology costs. Without attention, IC fabrication will likely become the dominant energy consumer and source of carbon emissions over an IC's lifetime. We propose a scaled parameterized model for evaluating the environmental impacts of IC fabrication, which can scale from 130nm to 32nm technology and account for stepwise changes in process technologies. As an example of the type of analysis possible using this model we demonstrate the environmental impacts of changing the metal stack at these technology nodes. Our results indicate that based on the die area calculated from a commercial design flow and our parameterized model, changing the number of metal layers from eight to six layers results in an average savings in manufacturing energy of 9.5%, 13.8%, and 13% for 130nm, 90nm, and 65nm technologies, respectively, and, depending on scenario, it can take years for operational energy savings to makeup this difference.","PeriodicalId":133239,"journal":{"name":"2017 Eighth International Green and Sustainable Computing Conference (IGSC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122161895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yifan Wang, Xingzhou Zhang, Lu Chao, Lang Wu, Xiaohui Peng
{"title":"PowerAnalyzer: An energy-aware power monitor system aiming at energy-saving","authors":"Yifan Wang, Xingzhou Zhang, Lu Chao, Lang Wu, Xiaohui Peng","doi":"10.1109/IGCC.2017.8323568","DOIUrl":"https://doi.org/10.1109/IGCC.2017.8323568","url":null,"abstract":"To save the electrical energy in a household, it is essential to monitor where and how the power is consumed. To maximize the efficiency of energy conservation, it is necessary to make the running power low in the power monitor system, which the tradition systems pay less attention to. This paper presents PowerAnalyzer, an energy-aware system for monitoring running states and power of each household appliance plugged into power line from a single point detection. PowerAnalyzer takes steady-state current waveforms as the appliances signature, and uses the deep neural network (DNN) models to infer the running states and running power of household appliances. We focus on the energy consumption of PowerAnalyzer itself. The energy efficiency of PowerAnalyzer is optimized from these aspects: Using dynamic time intervals to collect electric data, replacing a cloud server with an edge node to process data, and transmitting differential data over a low power wireless protocol. The evaluation results show that PowerAnalyzer offers 3.45% average power metering error and 98.38% average accuracy of inferring running states of appliances. PowerAnalyzer draws less than 247mW static power and 304mW peak power.","PeriodicalId":133239,"journal":{"name":"2017 Eighth International Green and Sustainable Computing Conference (IGSC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125730807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sagar Saxena, Deekshith Shenoy Manur, M. Ahmed, A. Ganguly
{"title":"Energy-efficiency in interconnection fabrics for inter and intra-chip communication using Graphene-based THz-band antennas","authors":"Sagar Saxena, Deekshith Shenoy Manur, M. Ahmed, A. Ganguly","doi":"10.1109/IGCC.2017.8323603","DOIUrl":"https://doi.org/10.1109/IGCC.2017.8323603","url":null,"abstract":"Most computing platforms such as embedded systems to server blades comprise of multiple Systems-on-Chips (SoCs). Traditionally, these multichip platforms are interconnected using metal traces over a substrate such as a Printed Circuit Board (PCB). Communications in multichip platforms involves data transfer between internal nets and the peripheral I/O ports of the chips as well as across the PCB traces. This multi-hop communication leads to higher energy consumption, decrease in data bandwidth and increase in message latency. Novel devices based on graphene structures capable of establishing wireless links are explored in recent literature to provide high performance on-chip interconnections. In this work, we propose to extend Graphene-based wireless links to enable energy-efficient, phase-based chip-to-chip communication to create a seamless, wireless interconnection fabric for multichip systems. With cycle-accurate simulations we show that such a design with torus like folding based on THz links instead of global wires can outperform state-of-the-art wireline multichip systems.","PeriodicalId":133239,"journal":{"name":"2017 Eighth International Green and Sustainable Computing Conference (IGSC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132339226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Mitigating register pressure in GPU kernels for improved energy efficiency","authors":"Apan Qasem, Samuel Teich","doi":"10.1109/IGCC.2017.8323599","DOIUrl":"https://doi.org/10.1109/IGCC.2017.8323599","url":null,"abstract":"GPUs have become an integral part of modern HPC systems. As the HPC landscape moves toward over-provisioned systems with heterogeneous compute nodes, the importance of GPUs is likely to grow. Therefore, strategies for energy savings on these devices are of critical importance. In this paper, we examine the energy efficiency of the register file on current GPUs. We show that ineffective utilization of the register file not only degrades performance but also increases power consumption. To address this problem, we develop a multi-level approach for mitigating register pressure in GPU kernels. Our strategy includes a source-to-source data layout transformation, a method for modulating register pressure (RP) via compiler optimizations, and an autotuner for selecting RP-sensitive kernel launch configurations. Experimental results show that our strategy is able to curb inefficiency in register file usage and can significantly boost performance and energy efficiency in a range of GPU kernels.","PeriodicalId":133239,"journal":{"name":"2017 Eighth International Green and Sustainable Computing Conference (IGSC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128788536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Ahmed, Md Shahriar Shamim, N. Mansoor, Sayed Ashraf Mamun, A. Ganguly
{"title":"Increasing interposer utilization: A scalable, energy efficient and high bandwidth multicore-multichip integration solution","authors":"M. Ahmed, Md Shahriar Shamim, N. Mansoor, Sayed Ashraf Mamun, A. Ganguly","doi":"10.1109/IGCC.2017.8323583","DOIUrl":"https://doi.org/10.1109/IGCC.2017.8323583","url":null,"abstract":"With the increase in number of processing chips in platform based computation intensive systems such as servers, a seamless, scalable, energy efficient and high bandwidth interconnection network is required. Newly envisioned silicon interposers with Network-on-Chip (NoC) interconnection framework have emerged as an energy efficient technology for 2.5D integration of multiple processor and memory chips, where multiple chips are mounted on another die called the interposer and are interconnected using the metal layers of the interposer die. However, conventional interposer based multichip integration is limited to edge-to-edge connections between the adjacent dies leaving the interposer's routing resources underutilized. In this paper, we propose large scale utilization of the available abundant interposer resources for multichip integration by implementing a hypercube interconnection architecture in an interposer for chip-to-chip communication. Through system level simulations, we demonstrate that such multichip system integrated with interposer can provide high bandwidth and energy-efficient communication under various traffic patterns.","PeriodicalId":133239,"journal":{"name":"2017 Eighth International Green and Sustainable Computing Conference (IGSC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115349788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Li Li, Bruce Beitman, Mai Zheng, Xiaorui Wang, Feng Qin
{"title":"eDelta: Pinpointing energy deviations in smartphone apps via comparative trace analysis","authors":"Li Li, Bruce Beitman, Mai Zheng, Xiaorui Wang, Feng Qin","doi":"10.1109/IGCC.2017.8323567","DOIUrl":"https://doi.org/10.1109/IGCC.2017.8323567","url":null,"abstract":"Many smartphone apps can consume an unnecessarily high amount of energy, shortening battery life. Although users can easily notice the undesired fast battery drain, it is almost impossible for them to precisely remember how the abnormal battery drain (ABD) is triggered, making it difficult for developers to fix the problem. Therefore, app developers are in an urgent need for a tool that can provide them helpful information. In this paper, we propose eDelta, a framework that assists developers in pinpointing the APIs with high energy deviation, which usually have a high probability of being relevant to the non-deterministic ABD. Specifically, eDelta performs comparative trace analysis to identify APIs that have significant energy consumption deviation in different user traces. With the information provided by eDelta, developers can substantially reduce the time they spend searching for the ABD root causes. We have prototyped eDelta in Android 4.4 and evaluated it with twenty real-world apps. Our results show that eDelta can effectively pinpoint the APIs with high energy deviation and those APIs indeed cause ABD. Specifically, it reduces, on average, 94.6% of the amount of code that the developers would need to search for ABD root causes.","PeriodicalId":133239,"journal":{"name":"2017 Eighth International Green and Sustainable Computing Conference (IGSC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127781022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}