Sustainable IC design and fabrication

Abstract

Low-energy computing in the use phase is compelling because it helps to address thermal density issues of deeply scaled CMOS, maximizes battery-life of mobile computing platforms, while also addressing sustainability. Unfortunately, environmental impacts of fabricating CMOS integrated circuits (ICs) is increasing and rapidly catching the operational phase of computing systems, particularly for low-energy and mobile computing products. This is due to trends in fabrication techniques for increasingly small geometries, such as increasing photo-lithography and metrology costs. Without attention, IC fabrication will likely become the dominant energy consumer and source of carbon emissions over an IC's lifetime. We propose a scaled parameterized model for evaluating the environmental impacts of IC fabrication, which can scale from 130nm to 32nm technology and account for stepwise changes in process technologies. As an example of the type of analysis possible using this model we demonstrate the environmental impacts of changing the metal stack at these technology nodes. Our results indicate that based on the die area calculated from a commercial design flow and our parameterized model, changing the number of metal layers from eight to six layers results in an average savings in manufacturing energy of 9.5%, 13.8%, and 13% for 130nm, 90nm, and 65nm technologies, respectively, and, depending on scenario, it can take years for operational energy savings to makeup this difference.