IEEE Transactions on Emerging Topics in Computing最新文献

{"title":"YAXY: A New Hybrid FPGA-Based Hardware Acceleration of TFHE","authors":"Yangfu Xu;Aijiao Cui;Xiangyu Guo;Yier Jin","doi":"10.1109/TETC.2026.3691777","DOIUrl":"https://doi.org/10.1109/TETC.2026.3691777","url":null,"abstract":"Fully Homomorphic Encryption (FHE) enables direct computation on ciphertexts, thereby ensuring data privacy during processing. However, its widespread application is impeded by high computational costs, with bootstrapping being a critical efficiency bottleneck. Torus FHE (TFHE) facilitates efficient evaluation of arbitrary Boolean functions via fast gate bootstrapping. This paper proposes YAXY, an FPGA-accelerated design for TFHE bootstrapping. It combines high-level synthesis (HLS) and register-transfer level (RTL) optimizations to improve performance. Our approach employs parameterized key unrolling and pipelined key transmission at the HLS level, coupled with a hierarchically pipelined RTL architecture designed to maximize parallelism in external product computations. Implemented on the Xilinx ZCU102 platform at 300 MHz, the design achieves a latency of 0.44 ms and a throughput of 2,273 bootstrappings per second. It offers the lowest-latency standalone FPGA TFHE bootstrapping. Compared to processor-based implementations, our accelerator exhibits superior speed-resource tradeoff. The results validate that HLS-RTL co-design can significantly enhance the practicality of FHE for privacy-preserving applications.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"14 2","pages":"649-661"},"PeriodicalIF":4.8,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148507563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"LOC-SAC: A Lyapunov-Guided Online Collaborative Offloading Strategy With the SAC Algorithm","authors":"Peiyan Yuan;Ming Li;Xiaoyan Zhao;Chenyang Wang;Hu Jin","doi":"10.1109/TETC.2026.3687572","DOIUrl":"https://doi.org/10.1109/TETC.2026.3687572","url":null,"abstract":"Lyapunov optimization plays a pivotal role in stabilizing systems and reducing energy consumption for online collaborative computing offloading. However, existing studies have encountered the issue of instantaneous greediness during the transformation process based on Lyapunov optimization, primarily due to the continuous operations involved in queue length calculations and local optimizations. This study investigates the application of soft actor-critic in optimizing the objective function of Lyapunov-guided queue models, aiming to achieve long-term and globally optimal offloading decisions. Firstly, the Lyapunov optimization framework is employed to build the service queue model and derive the upper bound of the system objective function. Secondly, the system action of resource allocation and the state space are constructed based on the queue model. Moreover, a deep reinforcement learning problem involving queue change and a Lyapunov drift-plus-penalty is formulated to minimize the system energy consumption. Thirdly, a queue-based internal discount factor is integrated into the system reward function of the SAC algorithm, enabling the system to achieve long-term gains more efficiently. Finally, an adaptive cloud-edge service offloading strategy is proposed to ensure queue stability and minimize energy consumption without necessitating a locally optimal solution at each time slot. Experimental results demonstrate that the proposed strategy exhibits superior scalability and robustness compared to other state-of-the-art and baseline approaches in online collaborative service offloading systems.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"14 2","pages":"588-603"},"PeriodicalIF":4.8,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148507959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Privacy-Preserving Outsourced Deep Neural Network Training: New Dual-Cloud Framework and Efficient Construction","authors":"Chen-Fan Chang;Kuan-Chun Huang;Bo-Jia Chen;Yu-Chi Chen","doi":"10.1109/TETC.2026.3676652","DOIUrl":"https://doi.org/10.1109/TETC.2026.3676652","url":null,"abstract":"Recently, deep neural networks (DNNs) have achieved excellent results in face recognition, natural language processing, and object classification. With the development of data science and the continuous increase in the size of datasets, the computing power and storage requirements for DNN training have also increased. Although GPUs and training methods have been continuously optimized for decades, the storage requirements remain a significant cost. To reduce the cost, datasets are often centrally placed in cloud storage for interactive training. Data security is undoubtedly the primary concern for such applications. Datasets for DNN training are usually collected by various institutions and often contain a lot of sensitive information. To prevent confidential information from leaking, data in cloud storage must be encrypted or protected. In this paper, we use secret sharing, a very lightweight method, to implement privacy-preserving outsourced DNN training. Using secret sharing, the data and models can be split into two shares and outsourced to two cloud service providers for training. Since the calculations are performed by the cloud service providers, the model trainer can be a device with limited computational power, such as a lightweight portable device.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"14 2","pages":"467-482"},"PeriodicalIF":4.8,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148509354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Efficient Ternary in-Memory Computing Architecture With Application in Phonocardiogram-Based Driver Stress Detection","authors":"Amirhossein Fathollahi;Nima Eslami;Mohammad Hossein Moaiyeri","doi":"10.1109/TETC.2026.3668394","DOIUrl":"https://doi.org/10.1109/TETC.2026.3668394","url":null,"abstract":"Traffic accidents remain a leading global cause of injury and fatalities, with driver stress identified as a significant contributing factor. Traditional stress detection methods, such as ECG-based systems, suffer from bulky designs and limited battery life, restricting their practicality for real-time wearable applications. To address these limitations, this paper presents a novel ternary in-memory computing (IMC) architecture for efficient PCG-based stress classification in power-constrained wearable devices. The proposed design introduces ternary full-adder and multiplier circuits based on emerging technologies, enabling energy-efficient neural network acceleration. Simulation results demonstrate that the proposed ternary full adder and multiplier designs reduce overall energy consumption by 98% on average compared to existing ternary counterparts. Furthermore, implementing a 1-D neural network for efficient stress classification, the proposed design achieves a 99% reduction in energy-delay-product (EDP). The results indicate that the proposed architecture is well-suited for power-constrained wearable devices in PCG-based stress detection applications.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"14 2","pages":"414-425"},"PeriodicalIF":4.8,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Time Information-Enhanced Multi-Space Modeling Spatiotemporal Transformer Network for Traffic Flow Forecasting","authors":"Bowen Yang;Zhizhe Lin;Jinglin Zhou;Hai Xie;Youyi Song;Teng Zhou","doi":"10.1109/TETC.2026.3680507","DOIUrl":"https://doi.org/10.1109/TETC.2026.3680507","url":null,"abstract":"Accurate traffic prediction is crucial for urban traffic planning and management. Recent advancements in spatiotemporal models have significantly improved the modeling of complex spatiotemporal correlations for traffic flow prediction. However, spatial correlations in traffic networks typically consist of both static and dynamic components. Many existing methods employ a single graph learning strategy to jointly model these components, which may limit their flexibility in comprehensively capturing the diverse spatial interactions among nodes. Additionally, the dynamic graph generation mechanisms based on input windows primarily rely on traffic flow observations within a limited time frame. This dependence on short-term observational data may hinder the effective capture of long-term spatiotemporal dependencies. To overcome these limitations, we propose a time information-enhanced multi-space modeling spatiotemporal transformer network (STMT) for traffic prediction. Specifically, we elaborate on three different spatiotemporal transformers for temporal modeling, static graph spatiotemporal modeling, and dynamic graph spatiotemporal dependency modeling to comprehensively model spatiotemporal relationships. Then, we design a dynamic graph generator that introduces a memory unit to provide historical traffic patterns during dynamic graph generation. Additionally, we propose time-node embeddings to adapt to different traffic patterns for the nodes at various times. Extensive experiments on six traffic datasets demonstrate that STMT achieves superior performance compared to 17 baseline methods.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"14 2","pages":"483-499"},"PeriodicalIF":4.8,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148509356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A New Quantum Efficient Fault Tolerant Parity Preserving Clifford + T ALU","authors":"Shekoofeh Moghimi;Mohammad Reza Reshadinezhad;Antonio Rubio","doi":"10.1109/TETC.2026.3696481","DOIUrl":"https://doi.org/10.1109/TETC.2026.3696481","url":null,"abstract":"Reversible logic is characterized by its feature of being a prominent application in low-power conventional computers and the most compatible logic in quantum computers. Quantum circuits executes quantum algorithms and are important in a new generation of advanced computing. However, they are highly error-prone and also subject to the use of limited and sensitive physical resources like qubits and quantum gates. This paper introduces a comprehensive fault tolerant quantum-based reversible circuit which can calculate a high variety number of arithmetic and logic operations. It uses both: parity preserving method for detecting one or an odd number of bit errors, and Clifford + T implementation for protecting circuits against decoherence faults. First, we propose a new fault-tolerant (parity preserving and Clifford + T) adder/subtractor and derive a quantum reversible Arithmetic and Logic Unit (ALU). These modules reach the most optimized extent of circuit line, ancilla inputs, and garbage outputs according to the logical analysis done in this work. This article focuses on reducing T-cost metrics in conjunction with enhancing the number of operations and quantum costs in proposed circuits compared to other counterparts. We propose 4-bit fault tolerant ALU derived from our proposed single-bit module to show the proposed circuit can be extended to any larger size. The proposed circuit is implemented in the Qiskit simulation tool, and output results confirm the accuracy of our design functionality. The proposed full adder/ subtractor achieves an average of 64% and 43%, and the proposed ALU circuit achieves an average of 38% and 27% improvement in T-count and T-depth, respectively compared to their counterparts. The proposed reversible quantum-optimized fault tolerant adder/subtractor and ALU units can be applied as the basic part of DSP systems and quantum processor units in quantum computing devices.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"14 2","pages":"718-733"},"PeriodicalIF":5.4,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11543196","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148236384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Emerging Topics in Computing Publication Information","authors":"","doi":"10.1109/TETC.2026.3696909","DOIUrl":"https://doi.org/10.1109/TETC.2026.3696909","url":null,"abstract":"","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"14 2","pages":"C2-C2"},"PeriodicalIF":4.8,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11561822","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148507963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Nomoformer: A Transformer-Based Approach for Pedestrian Trajectory Prediction With Non-Linear Motion Representation","authors":"Yuhao Qing;Yueying Wang;Hai Wang;Huaicheng Yan","doi":"10.1109/TETC.2026.3673699","DOIUrl":"https://doi.org/10.1109/TETC.2026.3673699","url":null,"abstract":"Multi-agent trajectory prediction plays a crucial role in various domains, including autonomous driving, uncrewed systems, and robotics. However, existing approaches have not fully addressed the complex interplay between motion patterns and multi-agent interaction features, making accurate trajectory prediction in complex scenarios particularly challenging. To address these limitations, we present Nomoformer, a transformer-based architecture for multi-agent trajectory prediction. Nomoformer predicts agent trajectories through joint analysis of motion representations and spatio-temporal interactions. Our approach first models individual agent dynamics by incorporating physical constraints derived from velocity and angular features. We mapped select motion features to the frequency domain to capture inherent relationships between periodic patterns and agent topology. To model inter-agent interactions, we developed a spatio-temporal graph topology using heterogeneous graphs with directed edge features and attention masks. Within this topology, we introduced Edge Encoder and Node Encoder modules that effectively establish long-range dependencies across edge features and temporal dimensions. Extensive experiments across multiple benchmarks demonstrated that Nomoformer achieved state-of-the-art performance in predicting future motion trajectories.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"14 2","pages":"456-466"},"PeriodicalIF":4.8,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"In-Memory Computing Paradigm Using Energy-Efficient Analog Arithmetic for DNA Sequence Alignment","authors":"Kavitha Soundrapandiyan;Bhupedra Singh Reniwal;Binsu J. Kailath","doi":"10.1109/TETC.2026.3672353","DOIUrl":"https://doi.org/10.1109/TETC.2026.3672353","url":null,"abstract":"To circumvent the bottleneck of energy efficiency in von Neumann architecture, research has focused on the computational methods within the memory array itself to accomplish in-memory computing (IMC). This work endorsed a novel analog IMC design framework for the bit addition employing 8<inline-formula><tex-math>$^+$</tex-math></inline-formula>T Static Random Access Memories (SRAM). With the principle of analog Full Adder (FA), other computations like ripple carry adder (RCA), multi-bit adder, subtractor and multiplier are accomplished for DNA Sequence Alignment use case. In contrast to traditional FAs, where addition is executed as a sequence of digital boolean operations and FA outputs computed using external logic gates, proposed analog adder leverages the bitline voltage discharge (V<inline-formula><tex-math>$_{BL}$</tex-math></inline-formula>) with regards to the data stored in the 8<inline-formula><tex-math>$^+$</tex-math></inline-formula>T memory cell. The implementation of the analog adder significantly reduces execution time in DNA Sequence Alignment. Extensive simulation results conducted using an industrial hardware-calibrated UMC 65nm CMOS technology demonstrate substantial improvements, including a 19 × to 27× reduction in power consumption and an 18× to 36× decrease in compute delay, resulting in a remarkable 342× to 972× reduction in energy consumption compared to ASA FA and MC FA under Process, Voltage, and Temperature (PVT) variations, achieving 10.6 TOPS/W. The 8<inline-formula><tex-math>$^+$</tex-math></inline-formula>T SRAM was characterized in the CACTI tool to facilitate system-level studies and ensure its accuracy, reliability, and effectiveness in the memory design. The proposed circuit's efficiency was evaluated by aligning chromosome sequences from human and chimpanzee genomes based on their similarity score. The proposed analog adder significantly reduces the execution time for sequence alignment when compared to RAPID with FELIX IMC. The proposed analog adder system achieves throughput improve ments of 56.8× and 2.6× over state-of-the-art CPU and GPU respectively.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"14 2","pages":"426-439"},"PeriodicalIF":4.8,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148509348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Practical and Efficient Non-Interactive Multi-Client Searchable Encryption for E-Healthcare Systems","authors":"Yanpeng Ba;Yuan Ping;Xiali Hei;Zheng Yuan","doi":"10.1109/TETC.2026.3692557","DOIUrl":"https://doi.org/10.1109/TETC.2026.3692557","url":null,"abstract":"In e-healthcare systems, the sensitivity of health data requires encryption before uploading to the cloud server, while also ensuring that healthcare service providers (HSPs) access only data within their authorized scope. To enable timely diagnoses, the system must minimize interactions during data retrieval. Additionally, it must efficiently verify the legitimacy of queries issued by potentially malicious HSPs to prevent unnecessary consumption of server resources. However, designing a system that simultaneously satisfies all these requirements remains a significant challenge. To address this, we propose a non-interactive multi-client dynamic searchable symmetric encryption (NIMC-DSSE) scheme tailored to the e-healthcare context. Specifically, our scheme employs a prefix-constrained pseudorandom function to ensure forward privacy in a non-interactive setting, and integrates a set-constrained pseudorandom function along with Bloom filters to enforce fine-grained access control and defend against malicious clients. The space-efficient nature of Bloom filters allows the server to maintain a complete update history with reasonable storage overhead, thereby enabling efficient time-range queries. Furthermore, we implemented the proposed scheme and conducted extensive experiments to compare it with state-of-the-art solutions. The experimental results show that our scheme achieves <inline-formula><tex-math>$7.24times$</tex-math></inline-formula> lower search latency on average, increasing to <inline-formula><tex-math>$17.25times$</tex-math></inline-formula> in the worst case. These improvements demonstrate that our work not only offers an effective new approach to designing secure and efficient NIMC-DSSE schemes, but also highlights their considerable potential in e-healthcare scenarios.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"14 2","pages":"662-677"},"PeriodicalIF":4.8,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}