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2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)最新文献

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CMOS sample-and-hold circuit using current conveyor analogue switch CMOS采样保持电路采用电流输送模拟开关
2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) Pub Date : 2016-10-01 DOI: 10.1109/ISPACS.2016.7824754
Thanat Nonthaputha, M. Kumngern, S. Lerkvaranyu
{"title":"CMOS sample-and-hold circuit using current conveyor analogue switch","authors":"Thanat Nonthaputha, M. Kumngern, S. Lerkvaranyu","doi":"10.1109/ISPACS.2016.7824754","DOIUrl":"https://doi.org/10.1109/ISPACS.2016.7824754","url":null,"abstract":"This paper presents a new CMOS sample-and-hold (S/H) circuit employing one second-generation current conveyor (CCII), one resistor and one capacitor. Unlike, conventional S/H circuits, the proposed S/H circuit is absent from MOS switches. The proposed S/H circuit uses CCII to work as analog switch (CCAS) which high speed on-off status of switch and without buffer circuit can be obtained. The status on-off of switch is controlled by bias current. This bias current is sampling pulse that used for sampling input signal. The proposed S/H circuit is suitable for low-power and high accuracy for signal processing applications. The simulation results are used to confirm the workability of the proposed circuit.","PeriodicalId":131543,"journal":{"name":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130865814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel design method of digital-digital sequences in DS/CDMA code-diversity systems DS/CDMA码分多址系统中数字-数字序列设计的一种新方法
2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) Pub Date : 2016-10-01 DOI: 10.1109/ISPACS.2016.7824709
S. Tachikawa, Hiroki Sanada
{"title":"A novel design method of digital-digital sequences in DS/CDMA code-diversity systems","authors":"S. Tachikawa, Hiroki Sanada","doi":"10.1109/ISPACS.2016.7824709","DOIUrl":"https://doi.org/10.1109/ISPACS.2016.7824709","url":null,"abstract":"This paper presents a novel design method of digital-digital sequence (DDS) for code-diversity systems in direct sequence / code division multiple access (DS/CDMA). In the DDS, both the branch sequences and the composite sequence can be constructed from digital signal, then, the code-diversity can be realized easily. To suppress interference effectively, the design method of arrangement in element sequences is needed for DDS. Sequential rearrangement is operated by evaluation for weight coefficients of diversity branches in training time. Desirable sequence design can be achieved shortly in this method. As a result, considerable improvements of bit error rate(BER) performances are shown by computer simulations.","PeriodicalId":131543,"journal":{"name":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121300327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Time frequency analysis: A sparse S transform approach 时频分析:一种稀疏S变换方法
2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) Pub Date : 2016-10-01 DOI: 10.1109/ISPACS.2016.7824713
Kashyap Patel, N. Kurian, N. George
{"title":"Time frequency analysis: A sparse S transform approach","authors":"Kashyap Patel, N. Kurian, N. George","doi":"10.1109/ISPACS.2016.7824713","DOIUrl":"https://doi.org/10.1109/ISPACS.2016.7824713","url":null,"abstract":"S transform, which is a powerful time frequency analysis method, has found applications in diverse areas of science and technology. The computational load offered by the S transform increases with increase in the length of the time series which is analysed. In an endeavour to reduce the computational load for time series which is sparse in the frequency domain, a new method for S transform computation is proposed in this paper. The new method uses an efficient search method to identify significant frequency indices and computes the S transform only at the selected frequency indices, thus reducing the computational burden. A simulation study has been carried out to test the efficiency of the proposed method for analytic and real-life signals. The proposed scheme has been shown to provide good signal reconstruction accuracy at a reduced computational load.","PeriodicalId":131543,"journal":{"name":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114111045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design of low power two bit magnitude comparator using adiabatic logic 采用绝热逻辑的低功耗二位幅度比较器设计
2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) Pub Date : 2016-10-01 DOI: 10.1109/ISPACS.2016.7824703
D. Kumar, M. Kumar
{"title":"Design of low power two bit magnitude comparator using adiabatic logic","authors":"D. Kumar, M. Kumar","doi":"10.1109/ISPACS.2016.7824703","DOIUrl":"https://doi.org/10.1109/ISPACS.2016.7824703","url":null,"abstract":"This paper reports a new design of low power two bit magnitude comparator with adiabatic logic in 0.18µm CMOS technology. The proposed design shows the improvement in power delay product (PDP) of 66.76% to 82.97% with varying power supply for 1.1V to 2.0V as compared to conventional design. PDP of proposed design shows an improvement of 73.98% to 81.15 % with temperature varying from 50°C to 10°C as compared to conventional design. Results show a significant improvement in terms of PDP for proposed design as compared to existing conventional designs.","PeriodicalId":131543,"journal":{"name":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133417907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Parallel morphological template matching design for efficient human detection application 并行形态学模板匹配设计用于高效的人体检测应用
2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) Pub Date : 2016-10-01 DOI: 10.1109/ISPACS.2016.7824675
T. Adiono, Radhian Ferel Armansyah, Fadhli Dzil Ikram, Swizya Satira Nolika, Rachmad Vidya Wicaksana Putra, A. H. Salman
{"title":"Parallel morphological template matching design for efficient human detection application","authors":"T. Adiono, Radhian Ferel Armansyah, Fadhli Dzil Ikram, Swizya Satira Nolika, Rachmad Vidya Wicaksana Putra, A. H. Salman","doi":"10.1109/ISPACS.2016.7824675","DOIUrl":"https://doi.org/10.1109/ISPACS.2016.7824675","url":null,"abstract":"In this paper, we present a VLSI design of human detection using Sum of Absolute Difference (SAD) based parallel morphological template matching method. Its research targets are to achieve small area consumption yet with fast computation. The architecture is designed to process original and its template images with resolution of 640×480 and 40×100 pixels respectively. Here, we propose two techniques, a rolling-index architecture for SAD computation and an optimized binary tree adder. For every calculation window, the difference between source and template is calculated in parallel processing. Hence, the SAD calculation computes 40×100 pixels per clock cycle. The proposed design is coded using Verilog HDL and implemented in Altera Cyclone II FPGA. The full processing time needs 307,200 clock cycles. Each image frame needs 6.144 ms and the frame speed reaches 162 frame-per-second (fps) for video application. This proposed design only consumes 16,689 logic elements, comprising 12,732 combinational functions and 4,460 dedicated logic registers.","PeriodicalId":131543,"journal":{"name":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124858045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A low-cost local cloud monitoring system 一个低成本的本地云监测系统
2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) Pub Date : 2016-10-01 DOI: 10.1109/ISPACS.2016.7824741
Thitinan Kliangsuwan, A. Heednacram
{"title":"A low-cost local cloud monitoring system","authors":"Thitinan Kliangsuwan, A. Heednacram","doi":"10.1109/ISPACS.2016.7824741","DOIUrl":"https://doi.org/10.1109/ISPACS.2016.7824741","url":null,"abstract":"In this paper, a local cloud monitoring station equipped with a fisheye lens camera is proposed and installed at Prince of Songkla University (PSU), Phuket. The station retrieves cloud images in conjunction with several meteorological sensors. The methodology and cloud classifier algorithm is proposed. The performance test using images captured from our cloud monitoring station shows that the cloud classification accuracy in practice is as high as 98.58%. The installed cloud monitoring system can report live cloud conditions and display them on a mobile application. Our complete system is inexpensive and suitable for local use of weather monitoring and alerting.","PeriodicalId":131543,"journal":{"name":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122203060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Stress direction and temperature detectable octagonal nMOSFET multi operation device 应力方向和温度可检测的八角形nMOSFET多操作装置
2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) Pub Date : 2016-10-01 DOI: 10.1109/ISPACS.2016.7824743
T. Harada, K. Kaiwa
{"title":"Stress direction and temperature detectable octagonal nMOSFET multi operation device","authors":"T. Harada, K. Kaiwa","doi":"10.1109/ISPACS.2016.7824743","DOIUrl":"https://doi.org/10.1109/ISPACS.2016.7824743","url":null,"abstract":"In this paper, we design, fabricate, and evaluate octagonal nMOSFET multi operation device for normal MOSFET operation, detection of 8 stress direction, and variation of temperatures. In previous works, one sensor device can detect only one physical or chemical phenomenon. If we get some sensing data, such as temperature, stress, and etc., more than two sensor devices must be implemented. According to stress detection, stress sensors reattach along stress direction for measurement, because most of the previous stress sensors can sense only one dimension. However, octagonal MOSFET is not necessary to adjust because this device has radial eight direction output terminals and can accommodate various sensing using these terminals. Furthermore, this device can also measure the variation of threshold voltage using these output terminals. For example, proposed device can get variety of temperatures due to the temperature characteristics of threshold voltage. As the results, we can realize that it can sense 8 stress directions and a variety of temperature.","PeriodicalId":131543,"journal":{"name":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":" 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120828330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Super-CORDIC: An approximation based parallel and redundant CORDIC algorithm 超级CORDIC:一种基于近似的并行冗余CORDIC算法
2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) Pub Date : 2016-10-01 DOI: 10.1109/ISPACS.2016.7824681
Tushar Supe, David V. Anderson
{"title":"Super-CORDIC: An approximation based parallel and redundant CORDIC algorithm","authors":"Tushar Supe, David V. Anderson","doi":"10.1109/ISPACS.2016.7824681","DOIUrl":"https://doi.org/10.1109/ISPACS.2016.7824681","url":null,"abstract":"This paper proposes an optimized and generalized Co-ordinate Rotation Digital Computer (CORDIC) algorithm in the rotation mode of the circular co-ordinate system. It computes the values of trigonometric functions and can be configured to provide the result with a lower overall latency than existing systems. This is done by using redundant representations and approximations of the required direction and angle of each rotation. The algorithm has been designed to provide the result in a fixed number of iterations equal to a design parameter as chosen by the designer. In each iteration, the algorithm performs rotations between zero and a certain number, in parallel. A technique to handle the scaling factor compensation for such an algorithm is also proposed. The results of the functional verification for different values of the design parameter and an estimation of the overall latency are presented.","PeriodicalId":131543,"journal":{"name":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":"45 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120839685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Rate-adaptive FF-LDGM code with selective inter-leaving scheme 具有选择性互留方案的速率自适应FF-LDGM码
2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) Pub Date : 2016-10-01 DOI: 10.1109/ISPACS.2016.7824760
T. Nakachi, T. Fujii
{"title":"Rate-adaptive FF-LDGM code with selective inter-leaving scheme","authors":"T. Nakachi, T. Fujii","doi":"10.1109/ISPACS.2016.7824760","DOIUrl":"https://doi.org/10.1109/ISPACS.2016.7824760","url":null,"abstract":"This paper introduces a rate-adaptive FireFort-LDGM (FF-LDGM) code for MMT adaptive Application Layer FEC (AL-FEC). The FF-LDGM code is an ISO/IEC MPEG international standard issued in Feb. 2015. It can handle a wade range of block lengths from a small number of packets to several thousands of packets. Especially, it is useful for real-time UHD video transmission. In this paper, we focus on recent advances in the rate adaptive FF-LDGM code. It provides a rate adaptive function that allows the coding rate to be adaptively changed to suit the network characteristic. We improve the error recovery performance of the rate-adaptive scheme by using selective interleaving. Simulation results demonstrate its superior adaptive performance.","PeriodicalId":131543,"journal":{"name":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":"43 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128532937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-performance noise tolerant comparator design for arithmetic circuits 用于算术电路的高性能耐噪比较器设计
2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) Pub Date : 2016-10-01 DOI: 10.1109/ISPACS.2016.7824678
P. Meher, K. Mahapatra
{"title":"High-performance noise tolerant comparator design for arithmetic circuits","authors":"P. Meher, K. Mahapatra","doi":"10.1109/ISPACS.2016.7824678","DOIUrl":"https://doi.org/10.1109/ISPACS.2016.7824678","url":null,"abstract":"This paper presents a low power noise tolerant comparator design for arithmetic circuits. Instead of using domino logic, this paper uses a modified domino logic style. This logic uses semi-domino logic style and some extra footer transistors which lead to minimize power dissipation and noise of the comparator. The new comparator is compared with the basic domino comparator in terms of noise tolerance, delay, power consumption and power-delay product. Simulation results show the advantage of proposed comparator on the basic domino comparator in terms of noise, delay, power consumption and power-delay product. The performance of both the comparator circuits are based on UMC 180nm CMOS process models with a supply voltage of 1.8V evaluated by the comparing of the simulation results obtained from Cadence specter. From the simulation results, it can be seen clearly that the proposed comparator is quite faster, low power consuming and more noise tolerant than the basic domino comparator.","PeriodicalId":131543,"journal":{"name":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131084352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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