{"title":"CMOS采样保持电路采用电流输送模拟开关","authors":"Thanat Nonthaputha, M. Kumngern, S. Lerkvaranyu","doi":"10.1109/ISPACS.2016.7824754","DOIUrl":null,"url":null,"abstract":"This paper presents a new CMOS sample-and-hold (S/H) circuit employing one second-generation current conveyor (CCII), one resistor and one capacitor. Unlike, conventional S/H circuits, the proposed S/H circuit is absent from MOS switches. The proposed S/H circuit uses CCII to work as analog switch (CCAS) which high speed on-off status of switch and without buffer circuit can be obtained. The status on-off of switch is controlled by bias current. This bias current is sampling pulse that used for sampling input signal. The proposed S/H circuit is suitable for low-power and high accuracy for signal processing applications. The simulation results are used to confirm the workability of the proposed circuit.","PeriodicalId":131543,"journal":{"name":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"CMOS sample-and-hold circuit using current conveyor analogue switch\",\"authors\":\"Thanat Nonthaputha, M. Kumngern, S. Lerkvaranyu\",\"doi\":\"10.1109/ISPACS.2016.7824754\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a new CMOS sample-and-hold (S/H) circuit employing one second-generation current conveyor (CCII), one resistor and one capacitor. Unlike, conventional S/H circuits, the proposed S/H circuit is absent from MOS switches. The proposed S/H circuit uses CCII to work as analog switch (CCAS) which high speed on-off status of switch and without buffer circuit can be obtained. The status on-off of switch is controlled by bias current. This bias current is sampling pulse that used for sampling input signal. The proposed S/H circuit is suitable for low-power and high accuracy for signal processing applications. The simulation results are used to confirm the workability of the proposed circuit.\",\"PeriodicalId\":131543,\"journal\":{\"name\":\"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPACS.2016.7824754\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPACS.2016.7824754","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
CMOS sample-and-hold circuit using current conveyor analogue switch
This paper presents a new CMOS sample-and-hold (S/H) circuit employing one second-generation current conveyor (CCII), one resistor and one capacitor. Unlike, conventional S/H circuits, the proposed S/H circuit is absent from MOS switches. The proposed S/H circuit uses CCII to work as analog switch (CCAS) which high speed on-off status of switch and without buffer circuit can be obtained. The status on-off of switch is controlled by bias current. This bias current is sampling pulse that used for sampling input signal. The proposed S/H circuit is suitable for low-power and high accuracy for signal processing applications. The simulation results are used to confirm the workability of the proposed circuit.