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[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic最新文献

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Heterojunction bipolar technology for emitter-coupled multiple-valued logic in gigahertz adders and multipliers 千兆赫加法器中发射器耦合多值逻辑的异质结双极技术
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic Pub Date : 1992-05-27 DOI: 10.1109/ISMVL.1992.186773
L. Micheel
{"title":"Heterojunction bipolar technology for emitter-coupled multiple-valued logic in gigahertz adders and multipliers","authors":"L. Micheel","doi":"10.1109/ISMVL.1992.186773","DOIUrl":"https://doi.org/10.1109/ISMVL.1992.186773","url":null,"abstract":"The use of advanced devices and emitter-coupled (EC) circuit techniques for implementing ultra-high-speed computer arithmetic is explored. Redundant encoding of the input digits and multiple-valued operands are used in the positive-digit and signed-digit number systems. Addition in both systems has only three steps and entails no carry propagation chains. Emitter-coupled multivalued logic (MVL) is presented. A novel literal circuit is included. SPICE simulations of AlGaAs/GaAs heterojunction bipolar transistor (HBT) integrated circuits resulted in 1.4-1.6-GHz clock performance estimates of the ECMVL building blocks. Advanced InP-based HBT technology development is proposed to attain 4-10-GHz adder and multiplier performance. Modified circuits using resonant tunneling diodes and transistors are also discussed.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132348776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Experiences of parallel processing with direct cover algorithms for multiple-valued logic minimization 用直接覆盖算法并行处理多值逻辑最小化的经验
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic Pub Date : 1992-05-27 DOI: 10.1109/ISMVL.1992.186780
Chyan Yang, Onur Oral
{"title":"Experiences of parallel processing with direct cover algorithms for multiple-valued logic minimization","authors":"Chyan Yang, Onur Oral","doi":"10.1109/ISMVL.1992.186780","DOIUrl":"https://doi.org/10.1109/ISMVL.1992.186780","url":null,"abstract":"The implementation of the direct cover algorithm, a heuristic, on a real parallel computer system, Intel iPSC/2, is reported. A CAD tool, HAMLET, that is based on direct cover algorithms has been ported to iPSC/2. Parallel neighborhood decoupling (PND), a parallel version of ND that runs faster than ND, is used, as well as another parallel implementation of ND, multibranch ND (Multi-ND), which allows each processor to search one path of the search tree until the number of processors is exhausted. Searching in multiple branches guarantees a higher probability of reaching an exact solution. In addition, Multi-ND uses less communication than PND, since once a process is assigned a task it will remain isolated from the host until there is a need to report its solution. The results show that Multi-ND outperforms PND in both optimality and speed.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134417941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A current-mode CMOS algorithmic analog-to-quaternary converter circuit 一种电流模式CMOS算法模拟-四元转换器电路
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic Pub Date : 1992-05-27 DOI: 10.1109/ISMVL.1992.186800
K. Current
{"title":"A current-mode CMOS algorithmic analog-to-quaternary converter circuit","authors":"K. Current","doi":"10.1109/ISMVL.1992.186800","DOIUrl":"https://doi.org/10.1109/ISMVL.1992.186800","url":null,"abstract":"A current-mode CMOS algorithmic analog-to-quaternary data converter circuit has been realized in a standard polysilicon-gate CMOS technology. This circuit accepts an analog current input and uses current comparators and pass gates to develop a set of quaternary, base-four, output currents. A single type of converter cell may be cascaded to the desired number of quaternary output digits. The reference current that defines the full scale input range may be set externally. This circuit is input-output compatible with other previously described VLSI-compatible current-mode CMOS quaternary threshold logic and memory circuits. The current-mode CMOS algorithmic analog-to-quaternary data converter circuit is presented, and its experimental and simulated performances are described.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129495511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Code assignment algorithm for highly parallel multiple-valued combinational circuits 高并行多值组合电路的代码分配算法
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic Pub Date : 1992-05-27 DOI: 10.1109/ISMVL.1992.186820
S. Tamaki, M. Kameyama, T. Higuchi
{"title":"Code assignment algorithm for highly parallel multiple-valued combinational circuits","authors":"S. Tamaki, M. Kameyama, T. Higuchi","doi":"10.1109/ISMVL.1992.186820","DOIUrl":"https://doi.org/10.1109/ISMVL.1992.186820","url":null,"abstract":"A multivalued code assignment algorithm for locally computable combinatorial circuits, when the functional specification for a permutation operation is given by the mapping relationship between input and output alphabets or symbols, is described. Partition theory, usually used in the design of sequential circuit, is effectively used for the fast search for the code assignment problem. Some examples are shown to demonstrate the usefulness of the algorithm.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121763313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A new balanced gate for structural testing 一种用于结构试验的新型平衡闸门
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic Pub Date : 1992-05-27 DOI: 10.1109/ISMVL.1992.186777
H. M. Razavi, P. Wong
{"title":"A new balanced gate for structural testing","authors":"H. M. Razavi, P. Wong","doi":"10.1109/ISMVL.1992.186777","DOIUrl":"https://doi.org/10.1109/ISMVL.1992.186777","url":null,"abstract":"A new circuit realization is presented for a family of gates that results in a simple test for structural integrity of a CMOS circuit. The gate during normal operation behaves like an ordinary CMOS gate. However, in the test mode a nominal voltage of 2.5 V on the inputs of the gate would result in a 2.5-V output if no stuck-at faults are present. A combinational circuit designed exclusively with this type of a gate can be tested for all stuck-at faults using a single test vector of 2.5 V on all primary inputs. It is shown that a 100% fault coverage is obtained at the gate level (90% at the transistor level) for a combinational circuit regardless of its size, function, and complexity.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130465618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On Yager's aggregation operators 关于Yager的聚合算子
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic Pub Date : 1992-05-27 DOI: 10.1109/ISMVL.1992.186833
H. J. Skala
{"title":"On Yager's aggregation operators","authors":"H. J. Skala","doi":"10.1109/ISMVL.1992.186833","DOIUrl":"https://doi.org/10.1109/ISMVL.1992.186833","url":null,"abstract":"R.R. Yager (1988) introduced a special type of aggregation operator, OWA operators, and applied them to multicriterion decision-making. An alternative definition of such operators is given. and their structural properties are investigated in some detail.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"49 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116317973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Defaults as first-class citizens 默认为一等公民
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic Pub Date : 1992-05-27 DOI: 10.1109/ISMVL.1992.186789
P. Doherty, W. Lukaszewicz
{"title":"Defaults as first-class citizens","authors":"P. Doherty, W. Lukaszewicz","doi":"10.1109/ISMVL.1992.186789","DOIUrl":"https://doi.org/10.1109/ISMVL.1992.186789","url":null,"abstract":"A nonmonotonic logic with explicit defaults, NML3, is presented. It is characterized by the following features: (1) the use of the strong Kleene three-valued logic as a basis; (2) the addition of an explicit default operator which enables distinguishing tentative conclusions from ordinary conclusions in the object language; and (3) the use of the idea of preferential entailment to generate nonmonotonic behavior. The central feature of the formalism, the use of an explicit default operator with a model-theoretic semantics based on the notion of a partial interpretation, distinguishes NML3 from most previous formalisms. By capitalizing on the distinction between tentative and ordinary conclusions, NML3 provides increased expressibility in comparison to many of the standard nonmonotonic formalisms and greater flexibility in the representation of subtle aspects of default reasoning. This is shown through examples.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125227398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Profiles of topics and authors of the international symposium on multiple-valued logic for 1971-1991 1971-1991年多值逻辑国际学术研讨会主题及作者简介
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic Pub Date : 1992-05-27 DOI: 10.1109/ISMVL.1992.186819
Susan W. Butler, J. T. Butler
{"title":"Profiles of topics and authors of the international symposium on multiple-valued logic for 1971-1991","authors":"Susan W. Butler, J. T. Butler","doi":"10.1109/ISMVL.1992.186819","DOIUrl":"https://doi.org/10.1109/ISMVL.1992.186819","url":null,"abstract":"The growth of multivalued logic over the 21-year period from 1971 through 1991, as indicated by papers in the International Symposium on Multiple-Valued Logic, is examined. Of specific interest are trends in research topics, including patterns of growth and decline. Also considered is the demographics of the contributing authors. This includes the distributions of authors by country, the percentage of authors who are new, the percentage of new authors who return, and the distribution of authors by affiliation (acedemia, industry, and government). To derive these statistics, a database of papers, authors, and topics was developed.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125342306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Binary input/ternary output switching circuits designed via the sign transformation 通过符号变换设计二进制输入/三元输出开关电路
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic Pub Date : 1992-05-27 DOI: 10.1109/ISMVL.1992.186816
P. Besslich, E. Trachtenberg
{"title":"Binary input/ternary output switching circuits designed via the sign transformation","authors":"P. Besslich, E. Trachtenberg","doi":"10.1109/ISMVL.1992.186816","DOIUrl":"https://doi.org/10.1109/ISMVL.1992.186816","url":null,"abstract":"Using the recently developed sign transformation as a design tool, a method for designing binary input/ternary output circuits is presented. It is shown how to combine sign coefficients into sign domain cubes in order to simplify the hardware structure. The implementation is based on a complete basis for all Boolean functions taking the values +1 and -1 for true and false values, respectively, and the value zero for unspecified conditions. Hardware realization requires some special devices. However, using present-day logic cell arrays, certain applications are possible.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114916496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Towards the realization of 4-valued CMOS circuits 实现4值CMOS电路
[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic Pub Date : 1992-05-27 DOI: 10.1109/ISMVL.1992.186784
Konrad Lei, Z. Vranesic
{"title":"Towards the realization of 4-valued CMOS circuits","authors":"Konrad Lei, Z. Vranesic","doi":"10.1109/ISMVL.1992.186784","DOIUrl":"https://doi.org/10.1109/ISMVL.1992.186784","url":null,"abstract":"Component-sharing is proposed to reduce the cost of four-valued one-variable CMOS circuits. An incremental algorithm that utilizes the newly defined basic blocks is used to compute a universal cost table. In particular, cost reduction from 6% to 29% is observed for 56 one-variable functions. The improvement is due to more effective use of circuit components. A current multiplexer for the synthesis of multivariable functions is proposed.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129414063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
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