{"title":"Comparison of diodes and resistors for measuring chip temperature during thermal characterization of electronic packages using thermal test chips","authors":"A. Claassen, H. Shaukatullah","doi":"10.1109/STHERM.1997.566797","DOIUrl":"https://doi.org/10.1109/STHERM.1997.566797","url":null,"abstract":"Thermal test chips are specially designed and built for thermal characterization of electronic packages. These chips have heaters for powering the chip and temperature sensors for measuring the chip temperature. One type of temperature sensor in wide use is a diode. Small resistors (also known as resistance temperature detectors or RTDs) are also used for measuring the chip temperature. This paper reviews and compares the characteristics of the diodes and RTDs used for chip temperature measurement during the thermal characterization of electronic packages. Techniques for reducing the measurement errors associated with these chip temperature sensors are also discussed. It is shown that the temperature versus voltage characteristics of RTDs at constant current are much more linear than those of diodes.","PeriodicalId":126120,"journal":{"name":"Thirteenth Annual IEEE. Semiconductor Thermal Measurement and Management Symposium","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121682591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Evaluation of isothermal and isoflux natural convection coefficient correlations for utilization in electronic package level thermal analysis","authors":"B. Zahn, R. Stout","doi":"10.1109/STHERM.1997.566779","DOIUrl":"https://doi.org/10.1109/STHERM.1997.566779","url":null,"abstract":"A 20-lead heatsink small outline package (20HSOP) was modeled on both an FR4 and aluminum printed circuit board using a solid model finite element simulation tool. Three different correlations (isothermal, single surface isoflux, and dual surface isoflux) were utilized to define the surface convection coefficients of both the package and printed circuit board in a natural convection cooled environment. Solid model temperature results were compared to physical measurements in order to evaluate the usefulness of the individual convection coefficient correlations for package level thermal analysis. Both the experimental and solid model simulation results were also compared to those obtained from an identical computational fluid dynamics (CFD) model of the 20HSOP package. The isothermal convection coefficient correlations provided the most accurate solid model simulation results (within 12%) when using the FR4 thermal characterization test board. The isoflux dual surface convection coefficient correlations provided the most accurate solid model simulation results (within 13%) when using the aluminum thermal characterization test board. Solid model solutions closely matched, and in some cases exceeded, the accuracy of the CFD model. The significance of these results to package level thermal analysis is discussed.","PeriodicalId":126120,"journal":{"name":"Thirteenth Annual IEEE. Semiconductor Thermal Measurement and Management Symposium","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129057750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Thermal analysis of a chip on board (COB)","authors":"J. De Moerloose, W. Temmerman","doi":"10.1109/STHERM.1997.566788","DOIUrl":"https://doi.org/10.1109/STHERM.1997.566788","url":null,"abstract":"While solving many of today's chip interconnection problems, MCM technology presents major challenges with respect to thermal compatibility. The high power dissipation on a very limited area in many cases forces additional cooling measures such as thermal vias and heat sinks. Whether such measures should be applied or not and, if so, where to apply them, are just some of the questions that have to be answered in the design process. Fortunately, new tools are coming to the aid of the designer. Current CFD software has evolved in such a way that a detailed simulation of a single chip on the scale of a module is no longer beyond our reach. In this paper we present a set of simulations (using the CFD software FLOTHERM) that were performed on a typical chip-on-board implementation of a clock function for a broadband fine-board. Junction temperatures are calculated for different types of heat sinks. In the second part of the paper, some experiments on a thermal test module are described and the thermal resistance of each chip was determined for different MCM-L thermal technologies.","PeriodicalId":126120,"journal":{"name":"Thirteenth Annual IEEE. Semiconductor Thermal Measurement and Management Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130148972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Issues in validating package compact thermal models for natural convection cooled electronic systems","authors":"V. Adams, D. Blackburn, Y. Joshi, D. Berning","doi":"10.1109/STHERM.1997.566778","DOIUrl":"https://doi.org/10.1109/STHERM.1997.566778","url":null,"abstract":"A methodology is proposed for the validation of compact thermal models of electronic packages which utilizes data and simulations obtained from a simple but realistic system containing the package. The test system is the enclosure specified by the JEDEC Subcommittee, JC15.1 for thermal measurements in a natural convection environment. Simulations for a detailed model and several different compact models for a 88-pin plastic quad flat-package in the enclosure are in good agreement with experimental measurements of junction temperature. The study shows that the system must be well characterized, including accurate knowledge of circuit board thermal conductivity and accurate simulation of radiation heat transfer, to serve for validation purposes. For the package used in this study, system level considerations can outweigh package level considerations for predicting junction temperature. Given that the system is accurately modeled, the JEDEC enclosure can serve as a viable experimental validation tool for compact models.","PeriodicalId":126120,"journal":{"name":"Thirteenth Annual IEEE. Semiconductor Thermal Measurement and Management Symposium","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122213480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Rosten, J. Parry, C. Lasance, H. Vinke, W. Temmerman, W. Nelemans, Y. Assouad, T. Gautier, O. Slattery, C. Cahill, M. O'Flattery, C. Lacaze, P. Zemlianoy
{"title":"Final report to SEMITHERM XIII on the European-funded project DELPHI-the development of libraries and physical models for an integrated design environment","authors":"H. Rosten, J. Parry, C. Lasance, H. Vinke, W. Temmerman, W. Nelemans, Y. Assouad, T. Gautier, O. Slattery, C. Cahill, M. O'Flattery, C. Lacaze, P. Zemlianoy","doi":"10.1109/STHERM.1997.566785","DOIUrl":"https://doi.org/10.1109/STHERM.1997.566785","url":null,"abstract":"The accurate prediction of the operating temperatures of critical electronic parts at the component-, board- and system-level is seriously hampered by the lack of reliable, standardised input data. This paper is the final report on the 3-year European collaborative project, named DELPHI, whose goal is to solve the aforementioned problem. The project concerns the creation and experimental validation of thermal models (detailed and compact) of a range of electronic parts including mono-chip packages, heat sinks, electrolytic capacitors, transformers and interfacing materials. The purpose of this paper is to give an account of the principal project results. Fuller details of the topics covered can be found in the papers listed in the DELPHI bibliography that is provided at the end of this paper.","PeriodicalId":126120,"journal":{"name":"Thirteenth Annual IEEE. Semiconductor Thermal Measurement and Management Symposium","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127641976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Thermal characterization of chip packages-evolutionary development of compact models","authors":"A. Bar-Cohen, W. Krueger","doi":"10.1109/STHERM.1997.566796","DOIUrl":"https://doi.org/10.1109/STHERM.1997.566796","url":null,"abstract":"The expanded-R/sub jc/ methodology, first proposed in 1989, makes it possible to extend the use of this common figure-of-merit to chip packages with non-isothermal cases. This proposal spurred considerable debate and contributed to renewed efforts to provide \"compact\" thermal models of single chip packages, for preliminary design, as well as for detailed numerical simulation of populated printed circuit boards. This work offers a review of the development of this modified-R/sub jc/ methodology and its efficacy in replicating the chip, or junction temperature predicted by detailed numerical simulation.","PeriodicalId":126120,"journal":{"name":"Thirteenth Annual IEEE. Semiconductor Thermal Measurement and Management Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129092419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multiobjective optimization of component placement on planar printed wiring boards","authors":"N. Queipo, G.F. Gil","doi":"10.1109/STHERM.1997.566786","DOIUrl":"https://doi.org/10.1109/STHERM.1997.566786","url":null,"abstract":"This paper presents a solution methodology for the optimal placement of convectively and conductively air-cooled electronic components on planar printed wiring boards considering thermal and electrical/cost design objectives. The methodology combines the use of a heat transfer solver for the prediction of the temperature distribution among the electronic components and a genetic algorithm for the adaptive search of optimal or near optimal solutions and a multiobjective optimization strategy (Pareto optimization and Multiattribute utility analysis). After proper validation of the elements of the solution methodology (heat transfer solver/genetic algorithm) in isolation, the methodology under consideration is tested using a placement problem (case study) that considers as optimization criteria the minimization of an estimate of the failure rate of the system of components due to thermal overheating (via an Arrhenius relation) and the minimization of the total wiring length (given some interconnectivity requirements). Results corresponding to the case study are presented and discussed for both Pareto optimization and Multiattribute utility analysis.","PeriodicalId":126120,"journal":{"name":"Thirteenth Annual IEEE. Semiconductor Thermal Measurement and Management Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134490937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}