2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献_第8页

Lightening Asynchronous Pipeline Controller Through Resynthesis and Optimization 基于再合成与优化的异步管道控制器

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045358

Jeongwoo Heo, Taewhan Kim

{"title":"Lightening Asynchronous Pipeline Controller Through Resynthesis and Optimization","authors":"Jeongwoo Heo, Taewhan Kim","doi":"10.1109/ASP-DAC47756.2020.9045358","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045358","url":null,"abstract":"A bundled-data asynchronous circuit is a promising alternative to a synchronous circuit for implementing high performance low power systems, but it requires to deploy special circuitry to support the asynchronous communication between every pair of consecutive pipeline stages. This work addresses the problem of reducing the size of asynchronous pipeline controller. Lightening the pipeline controller directly impacts two critical domains: (1) it mitigates the increase of controller area caused by high process-voltage-temperature variation on circuit; (2) it contributes to proportionally reducing the leakage power. (Note that a long delay in circuit between pipeline stages requires a long chain of delay elements in the controller.) Precisely, we analyze the setup timing paths on the conventional asynchronous pipeline controller, and (i) resynthesize new setup timing paths, which allows to share some of the expensive delay elements among the paths while assuring the communication correctness. Then, we (ii) optimally solve the problem of minimizing the number of delay elements by formulating it into a linear programming. For a set of test circuits with a 45nm standard cell library, it is shown that our synthesis and optimization method reduces the total area of delay elements and the leakage power of pipeline controller by 46.4% and 43.6% on average, respectively, while maintaining the same level of performance and dynamic power consumption.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127078864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

iGPU Leak: An Information Leakage Vulnerability on Intel Integrated GPU iGPU Leak:针对Intel集成GPU的信息泄露漏洞

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045745

Wenjian He, Wei Zhang, Sharad Sinha, Sanjeev Das

引用次数: 2

Maximizing the Communication Parallelism for Wavelength-Routed Optical Networks-On-Chips 最大化波长路由光网络片上通信并行性

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045163

Mengchu Li, Tsun-Ming Tseng, Mahdi Tala, Ulf Schlichtmann

{"title":"Maximizing the Communication Parallelism for Wavelength-Routed Optical Networks-On-Chips","authors":"Mengchu Li, Tsun-Ming Tseng, Mahdi Tala, Ulf Schlichtmann","doi":"10.1109/ASP-DAC47756.2020.9045163","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045163","url":null,"abstract":"Enabled by recent development in silicon photonics, wavelength-routed optical networks-on-chips (WRONoCs) emerge as an appealing next-generation architecture for the communication in multiprocessor system-on-chip. WRONoCs apply a passive routing mechanism that statically reserves all data transmission paths at design time, and are thus able to avoid the latency and energy overhead for arbitration, compared to other ONoC architectures. Current research mostly assumes that in a WRONoC topology, each initiator node sends one bit at a time to a target node. However, the communication parallelism can be increased by assigning multiple wavelengths to each path, which requires a systematic analysis of the physical parameters of the silicon microring resonators and the wavelength usage among different paths. This work proposes a mathematical modeling method to maximize the communication parallelism of a given WRONoC topology, which provides a foundation for exploiting the bandwidth potential of WRONoCs. Experimental results show that the proposed method significantly outperforms the state-of-the-art approach, and is especially suitable for application-specific WRONoC topologies.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124592529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

AIR: A Fast but Lazy Timing-Driven FPGA Router AIR:一种快速但懒惰的时序驱动FPGA路由器

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045175

Kevin E. Murray, Sheng Zhong, Vaughn Betz

引用次数: 19

Analyzing The Security of The Cache Side Channel Defences With Attack Graphs 用攻击图分析缓存侧通道防御的安全性

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045664

Limin Wang, Ziyuan Zhu, Zhanpeng Wang, Dan Meng

引用次数: 4

Emerging Non-Volatile Memories for Computation-in-Memory 用于内存计算的新兴非易失性存储器

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045394

B. Gao

引用次数: 3

Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core Systems 异构多核系统中非功能性应用需求的运行时实施

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045536

J. Teich, Behnaz Pourmohseni, Oliver Keszöcze, J. Spieck, S. Wildermann

{"title":"Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core Systems","authors":"J. Teich, Behnaz Pourmohseni, Oliver Keszöcze, J. Spieck, S. Wildermann","doi":"10.1109/ASP-DAC47756.2020.9045536","DOIUrl":"https://doi.org/10.1109/ASP-DAC47756.2020.9045536","url":null,"abstract":"For many embedded applications, non-functional requirements such as safety, reliability, and execution time must be guaranteed in tight bounds on a given multi-core platform. Here, jitter in non-functional program execution qualities is caused either by outer influences such as faults injected by the environment, but can be induced also from the system management software itself, including thread-to-core mapping, scheduling and power management. A second huge source of variability typically stems from data-dependent workloads. In this paper, we classify and present techniques to enforce nonfunctional execution properties on multi-core platforms. Based on a static design space exploration and analysis of influences of variability of non-functional properties, enforcement strategies are generated to guide the execution of periodically executed applications in given requirement corridors. Using the case study of a complex image streaming application, we show that by controlling DVFS settings of cores proactively, not only tight execution times, but also reliability requirements may be enforced dynamically while trying to minimize energy consumption.","PeriodicalId":125112,"journal":{"name":"2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133725171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Standard-compliant Parallel SystemC simulation of Loosely-Timed Transaction Level Models 符合标准的松散时间事务级模型的并行系统仿真

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045568

Gabriel Busnot, Tanguy Sassolas, N. Ventroux, M. Moy

引用次数: 5

PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network PowerNet:基于最大卷积神经网络的可转移动态红外降估计

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045574

Zhiyao Xie, Haoxing Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen

引用次数: 39

Automated Test Generation for Activation of Assertions in RTL Models RTL模型中断言激活的自动测试生成

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2020-01-01 DOI: 10.1109/ASP-DAC47756.2020.9045731

Yangdi Lyu, P. Mishra

引用次数: 22